isp1564 NXP Semiconductors, isp1564 Datasheet - Page 52

• Manufacturer Part Number: isp1564
• Description: Isp1564 Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 78.
Address: Content of the base address register + 38h
Table 79.
Address: Content of the base address register + 3Ch
[1]
Table 80.
Address: Content of the base address register + 3Ch
ISP1564_1
Product data sheet
Bit
31
30 to 14
13 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 14
13 to 0
The reserved bits must always be written with the reset value.
Symbol
reserved
FN[13:0]
HcFmRemaining - Host Controller Frame Remaining register bit description
HcFmNumber - Host Controller Frame Number register bit allocation
HcFmNumber - Host Controller Frame Number register bit description
11.1.16 HcFmNumber register
Symbol
FRT
reserved
FR[13:0]
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
reserved
This register is a 16-bit counter, and the bit allocation is given in
timing reference among events happening in the Host Controller and the HCD. The HCD
may use the 16-bit value specified in this register and generate a 32-bit frame number,
without requiring frequent access to the register.
Description
-
Frame Number: Incremented when HcFmRemaining is reloaded. It must be rolled over to 0h after
FFFFh. Automatically incremented when entering the USBOPERATIONAL state. The content is
written to HCCA after the Host Controller has incremented Frame Number at each frame boundary
and sent an SOF but before the Host Controller reads the first ED in that frame. After writing to
HCCA, the Host Controller sets SF (bit 2 in HcInterruptStatus).
Description
Frame Remaining Toggle: This bit is loaded from FIT (bit 31 of HcFmInterval) whenever
FR[13:0] reaches 0. This bit is used by the HCD for the synchronization between FI[13:0]
(bits 13 to 0 of HcFmInterval) and FR[13:0].
-
Frame Remaining: This counter is decremented at each bit time. When it reaches 0, it is reset by
loading the FI[13:0] value specified in HcFmInterval at the next bit time boundary. When entering
the USBOPERATIONAL state, the Host Controller reloads the content with FI[13:0] of
HcFmInterval and uses the updated value from the next SOF.
[1]
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Rev. 01 — 4 December 2006
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
reserved
reserved
FN[7:0]
[1]
[1]
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
FN[13:8]
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
HS USB PCI Host Controller
Table
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
79. It provides a
© NXP B.V. 2006. All rights reserved.
ISP1564
R/W
R/W
R/W
R/W
24
16
0
0
8
0
0
0
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