isp1564 NXP Semiconductors, isp1564 Datasheet - Page 48
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isp1564
Manufacturer Part Number
isp1564
Description
Isp1564 Hi-speed Universal Serial Bus Pci Host Controller
Manufacturer
NXP Semiconductors
Datasheet
1.ISP1564.pdf
(99 pages)
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NXP Semiconductors
[1]
Table 70.
Address: Content of the base address register + 28h
Table 71.
Address: Content of the base address register + 2Ch
ISP1564_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
31 to 4
3 to 0
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits must always be written with the reset value.
Symbol
BHED[27:0]
reserved
HcBulkHeadED - Host Controller Bulk Head Endpoint Descriptor register bit description
HcBulkCurrentED - Host Controller Bulk Current Endpoint Descriptor register bit allocation
11.1.12 HcBulkCurrentED register
R/W
R/W
R/W
R/W
R/W
R/W
23
15
31
23
15
0
0
7
0
0
0
0
This register contains the physical address of the current endpoint of the bulk list. The
endpoints are ordered according to their insertion to the list because the bulk list must be
served in a round-robin fashion.
The bit allocation is given in
Description
Bulk Head ED: The Host Controller traverses the bulk list starting with the HcBulkHeadED pointer.
The content is loaded from HCCA during the initialization of the Host Controller.
-
R/W
R/W
R/W
R/W
R/W
R/W
22
14
30
22
14
0
0
6
0
0
0
0
BHED[3:0]
R/W
R/W
R/W
R/W
R/W
R/W
21
13
29
21
13
0
0
5
0
0
0
0
Rev. 01 — 4 December 2006
Table
R/W
R/W
R/W
R/W
R/W
R/W
20
12
28
20
12
0
0
4
0
0
0
0
BHED[19:12]
BCED[27:20]
BCED[19:12]
BHED[11:4]
BCED[11:4]
71.
R/W
R/W
R/W
R/W
R/W
R/W
19
11
27
19
11
0
0
3
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
18
10
26
18
10
0
0
2
0
0
0
0
HS USB PCI Host Controller
reserved
[1]
R/W
R/W
R/W
R/W
R/W
R/W
17
25
17
0
9
0
1
0
0
0
9
0
© NXP B.V. 2006. All rights reserved.
ISP1564
R/W
R/W
R/W
R/W
R/W
R/W
16
24
16
0
8
0
0
0
0
0
8
0
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