isp1564 NXP Semiconductors, isp1564 Datasheet - Page 85

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isp1564

Manufacturer Part Number
isp1564
Description
Isp1564 Hi-speed Universal Serial Bus Pci Host Controller
Manufacturer
NXP Semiconductors
Datasheet

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NXP Semiconductors
Table 134. PCI clock and IO timing
V
Typical values are at V
[1]
ISP1564_1
Product data sheet
Symbol Parameter
PCI clock timing; see
T
t
t
SR
SR
PCI input timing; see
t
t
t
PCI output timing; see
t
t
t
t
PCI reset timing
t
t
high
low
su
su(ptp)
h
val
val(ptp)
dZH
dHZ
rst
rst-clk
Fig 8. USB source differential data-to-EOP transition skew and EOP width
CC(IO)
cyc
CLK
RST#
REQ# and GNT# are point-to-point signals. GNT# has a setup of 10 ns; REQ# has a setup of 12 ns. All others are bus signals.
= 3.0 V to 3.6 V; T
+3.3 V
T
CLK cycle time
CLK HIGH time
CLK LOW time
CLK slew rate
RST# slew rate
input set-up time to CLK - bused signals
input set-up time to CLK - point-to-point
input hold time from CLK
CLK to signal valid delay time - bused signals
CLK to signal valid delay time - point-to-point
float to active HIGH delay time
active HIGH to float delay time
reset active time after power stable
reset active time after CLK stable
differential
data lines
0 V
PERIOD
T
15.1 Timing
is the bit duration corresponding to the USB data rate.
PERIOD
CC(IO)
Figure 10
Figure 9
Figure 11
amb
= 3.3 V; T
= 40 C to +85 C; unless otherwise specified.
crossover point
N
N
differential data to
SE0/EOP skew
T
T
amb
PERIOD
PERIOD
= +25 C; unless otherwise specified.
+ t
+ t
FDEOP
LDEOP
Rev. 01 — 4 December 2006
Conditions
crossover point
extended
[1]
[1]
Min
30
11
11
1
50
7
10
0
2
2
2
-
1
100
source EOP width: t
receiver EOP width: t
HS USB PCI Host Controller
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
FEOPT
© NXP B.V. 2006. All rights reserved.
FEOPR
Max
32
-
-
4
-
-
-
-
11
12
-
28
-
-
ISP1564
, t
004aaa929
, t
LEOPT
LEOPR
Unit
ns
ns
ns
V/ns
mV/ns
ns
ns
ns
ns
ns
ns
ns
ms
85 of 99
s

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