isp1563 NXP Semiconductors, isp1563 Datasheet - Page 80

• Manufacturer Part Number: isp1563
• Description: Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 119. PORTSC 1, 2, 3, 4 - Port Status and Control, 1, 2, 3, 4 register bit description
Address: Content of the base address register + 64h + (4
ISP1563_2
Product data sheet
Bit
8
7
6
5
4
3
Symbol
PR
SUSP
FPR
OCC
OCA
PEDC
Description
Port Reset: Logic 1 means the port is in reset. Logic 0 means the port is not in reset. Default = 0.
When software sets this bit from logic 0, the bus reset sequence as defined in Universal Serial
Bus Specification Rev. 2.0 is started. Software clears this bit to terminate the bus reset sequence.
Software must hold this bit at logic 1 until the reset sequence, as specified in Universal Serial Bus
Specification Rev. 2.0 , is completed.
Remark: When software sets this bit, it must also clear the Port Enable bit.
Remark: When software clears this bit, there may be a delay before the bit status changes to
logic 0 because it will not read logic 0 until the reset is completed. If the port is in high-speed
mode after reset is completed, the Host Controller will automatically enable this port; it can set the
Port Enable bit. A Host Controller must terminate the reset and stabilize the state of the port
within 2 ms of software changing this bit from logic 1 to logic 0. For example, if the port detects
that the attached device is high-speed during a reset, then the Host Controller must enable the
port within 2 ms of software clearing this bit.
HCH (bit 12 in the USBSTS register) must be logic 0 before software attempts to use this bit. The
Host Controller may hold Port Reset asserted when the HCH bit is set.
Suspend: Default = 0. Logic 1 means the port is in the suspend state. Logic 0 means the port is
not suspended. The PED (Port Enabled) bit and this bit define the port states as follows:
PED = 0 and SUSP = X — Port is disabled.
PED = 1 and SUSP = 0 — Port is enabled.
PED = 1 and SUSP = 1 — port is suspended.
When in the suspend state, downstream propagation of data is blocked on this port, except for the
port reset. If a transaction was in progress when this bit was set, blocking occurs at the end of the
current transaction. In the suspend state, the port is sensitive to resume detection. The bit status
does not change until the port is suspended and there may be a delay in suspending a port, if
there is a transaction currently in progress on USB. Attempts to clear this bit are ignored by the
Host Controller. The Host Controller will unconditionally set this bit to logic 0 when:
If the host software sets this bit when the Port Enabled bit is logic 0, the results are undefined.
Force Port Resume: Logic 1 means resume detected or driven on the port. Logic 0 means no
resume (K-state) detected or driven on the port. Default = 0. Software sets this bit to drive the
resume signaling. The Host Controller sets this bit if a J-to-K transition is detected, while the port
is in the suspend state. When this bit changes to logic 1 because a J-to-K transition is detected,
PCD (bit 2 in register USBSTS) is also set to logic 1. If software sets this bit to logic 1, the Host
Controller must not set bit PCD. When the EHCI controller owns the port, the resume sequence
follows the sequence given in Universal Serial Bus Specification Rev. 2.0 . The resume signaling
(full-speed ‘K’) is driven on the port as long as this bit remains set. Software must time the resume
and clear this bit after the correct amount of time has elapsed. Clearing this bit causes the port to
return to high-speed mode, forcing the bus below the port into a high-speed idle. This bit will
remain at logic 1, until the port has switched to the high-speed idle. The Host Controller must
complete this transition within 2 ms of software clearing this bit.
Overcurrent Change: Default = 0. This bit is set to logic 1 when there is a change in overcurrent
active. Software clears this bit by setting this bit to logic 1.
Overcurrent Active: Default = 0. If set to logic 1, this port has an overcurrent condition. If set to
logic 0, this port does not have an overcurrent condition. This bit will automatically change from
logic 1 to logic 0 when the overcurrent condition is removed.
Port Enable/Disable Change: Logic 1 means the port enabled or disabled status has changed.
Logic 0 means no change. Default = 0. For the root hub, this bit is set only when a port is disabled
because of the appropriate conditions existing at the EOF2 point. For definition of port error, refer
to Universal Serial Bus Specification Rev. 2.0 , Chapter 11. Software clears this bit by setting it.
•
•
Software changes the FPR (Force Port Resume) bit to logic 0.
Software changes the PR (Port Reset) bit to logic 1.
Rev. 02 — 15 March 2007
Port Number
1) where Port Number is 1, 2, 3, 4
[1]
HS USB PCI Host Controller
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© NXP B.V. 2007. All rights reserved.
ISP1563
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