mc33905s Freescale Semiconductor, Inc, mc33905s Datasheet - Page 32

• Manufacturer Part Number: mc33905s
• Description: System Basis Chip Gen2 With High Speed Can And Lin Interface
• Manufacturer: Freescale Semiconductor, Inc

and conditions to enter or leave each modes are illustrated in
the state diagram.
INIT RESET
on”. In this mode, the RSTb pin is asserted low, for a duration
of typ 1ms. Control bits and flags are “set” to their default
reset condition. The BATFAIL is set to indicated that the
device is coming from an unpowered condition, and that all
previous device configuration are lost and “reset” the default
value. The duration of the INIT reset is typ 1ms.
the expected SPI command does not occur in due time (ref.
INIT mode), and if device is not in debug mode.
INIT
mode. In this mode, the device must be configured via SPI
within a time of 256ms max.
and INIT MISC must be and can only be configured during
INIT mode.
can be also written in other modes.
Watchdog Refresh command must be send in order to set the
device into Normal mode. If the SPI W/D refresh does not
occur within the 256ms period, the device will return into INIT
reset mode for typ 1ms, and then re enter into INIT mode.
device status or to read back the INIT register configuration
is only possible to re enter the INIT mode using a secured SPI
command.
RESET
entered from Normal mode, Normal Request mode, LP V
on mode and from Flash mode, when the W/D is not
triggered, or if a VDD low condition is detected.
defined a longer Reset pulse activation only for the case the
reset mode is entered following a VDD low condition. Reset
pulse is always 1ms, in case Reset mode in entered due to
wrong W/D refresh command.
NORMAL REQUEST
after a wake up from Low Power V
NORMAL mode. The duration of the Normal request mode is
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33904/5
FUNCTIONAL DEVICE OPERATION
MODE AND STATE DESCRIPTION
The device has several operation modes. The transitions
This mode is automatically entered after device “power
INIT reset mode is also entered from INIT mode in case
This mode is automatically entered from “INIT reset”
Four registers called INIT Wdog, INIT REG, INIT LIN I/O
Other registers can be written in this mode, however they
Once the INIT registers configuration is done, a SPI
Register read operation is allowed in INIT mode to collect
When INIT mode is left by a SPI W/D refresh command, it
In this mode, the RSTb pin is asserted low. Reset mode is
The duration of reset is typ 1ms by default. The user can
Reset mode can be entered via secured SPI command.
This mode is automatically entered after RESET mode, or
A W/D refresh SPI command is necessary to transition to
DD
ON Mode.
FUNCTIONAL DEVICE OPERATION
MODE AND STATE DESCRIPTION
DD
256ms when Normal Request mode is entered after RESET
mode. Different duration can be selected by SPI for the case
when normal request is entered from LP V
256ms (or the shorter user defined time out), then the device
will enter into RESET mode, for a duration of typ 1ms.
well as in low power modes, the VDD external PNP is
disabled.
NORMAL
is entered by a SPI W/D refresh command from Normal
Request mode, or from INIT mode.
operating, and a periodic W/D refresh must occurs. In case of
incorrect or missing W/D refresh command device will enter
into Reset mode.
command into Low Power modes (Low Power V
Low Power V
commands must be used to enter from Normal mode in
RESET mode, INIT mode or FLASH mode.
FLASH
to typ 32 seconds. This allow programming of the MCU flash
memory while minimizing the software over head to refresh
the W/D. The flash mode is entered by Secured SPI
command and is left by SPI command. Device will enter into
RESET mode. In case of incorrect or missing W/D refresh
command device will enter into Reset mode. An INT can be
generated at 50% of the W/D period.
CAN bus, inside the vehicle.
DEBUG
allows system easy software and hardware debugging. The
debug operation is detected after power up if the DBG pin is
set in the 8.0-10V range.
operations are disabled: 256ms of INIT mode, W/D refresh of
Normal mode and Flash mode, Normal Request time out
(256ms or user defined value) are not operating and will not
lead to transition into INIT reset or Reset mode.
without any time constraints with respect to W/D operation,
MCU program can be “halted” or “paused” to verify proper
operation.
by SPI command (ref to MODE register).
If the W/D refresh SPI command does not occur within the
note: in init reset, init, reset and normal request modes as
In this mode, all device functions are available. This mode
During Normal mode, the device Watchdog function is
From Normal mode, the device can be set by SPI
In this mode, the software watchdog period is extended up
CAN interface operates in Flash mode to allow flash via
Debug is a special operation mode of the device which
When debug is detected, all the software watchdog
When device is in Debug, SPI command can be send
Debug can be left by removing 8-10V from debug pin, or
5V-CAN regulator is ON by default in debug mode.
DD
OFF Modes). Dedicated secured SPI
Analog Integrated Circuit Device Data
Freescale Semiconductor
DD
ON mode.
DD
ON or