mc33905s Freescale Semiconductor, Inc, mc33905s Datasheet - Page 33

• Manufacturer Part Number: mc33905s
• Description: System Basis Chip Gen2 With High Speed Can And Lin Interface
• Manufacturer: Freescale Semiconductor, Inc

Mode with VDD off, and Low Power Mode with VDD on.
up flags must be cleared (ref to Mode register).
LOW POWER - V
VDD is unsupplied. This mode is entered by the SPI. It can
also be entered by automatic transition due to fail safe
management. 5V-CAN and Vaux regulators are also turned
OFF.
monitors external events to wake up and leave the LP mode.
The wake up events can occurs from:
reset mode and then into Normal Request mode. The wake
up source are reported into the device SPI registers. In
summary, a wake up event from LP Vdd off, lead to Vdd
regulator turn ON, and MCU operation restart.
LOW POWER - V
5.0V (or 3.3V, depending upon device part number). The
objective is to maintain the MCU powered, with reduced
consumption. In such mode, the DC output current is
expected to be limited to few 100uA or few mA, as the ECU
is in reduced power operation mode.
are OFF.
Analog Integrated Circuit Device Data
Freescale Semiconductor
The device has two main Low Power Modes: Low Power
note: Prior to enter in Low Power mode, I/O and CAN wake
In this mode, VDD is turned off and the MCU connected to
When the device is in Low Power V
• CAN
• LIN interface, depending upon device part number
• Expiration of an internal timer
• I/O-0, and I/O-inputs, and depending upon device part
• Cyclic sense of I/O-1 input, associated by I/O-0
When a wake up event is detected, the device enters into
In this mode, the voltage at the VDD terminal remains at
During this mode, the 5V-CAN and V
number and configuration, I/O-2 and/or 3 input
activation, and depending upon device part number and
configuration, cyclic sense of I/O-2 and 3 input,
associated by I/O-0 activation
DD
DD
OFF
ON
DD
OFF Mode, it
AUX
regulators
LOW POWER MODES
LIN, I/O, timer, cyclic sense) are available in LP Vdd on
mode.
available.
several tenth of mA DC. The current source capability can be
time limited, by a selectable internal timer. Timer duration is
up to 32ms, and is triggered when the output current exceed
the output current threshold typ 1.5mA.
while the device remains in LP V
exceed the selected time (ex 32ms), the device will detect a
wake up.
pulse at INT pulse. The MCU will detect the INT pulse and
resume operation.
Watchdog function in LP V
ON Mode. In this case, the principle is time out.
LP Vdd on mode.
time out expired or voltage conditions), or via SPI command,
or by external event such as wake up. Some mode change
are performed via “secured” SPI commands.
The same wake-up events as in LP Vdd off mode (CAN,
In addition, two additional wake up conditions are
• Dedicated SPI command. When device is in LP Vdd ON
• Output current from Vdd exceeding typ 1.5mA
In Low Power V
This allow for instance a periodic activation of the MCU,
Wake up event are reported to the MCU via a low level
It is possible to enable the W/D function in Low Power V
Refresh of the W/D is done either by:
• a dedicated SPI command (different from any other SPI
• or by a temporary (less than 32ms max) Vdd over
As long as the W/D refresh occurs, the device remains in
MODE transition
mode transition are either done automatically (i.e after
mode, the wake up by SPI command uses a write to
“Normal Request Mode”, 0x5C10.
threshold.
command or simple CSb activation which would wake
up - ref to above paragraph)
current wake-up (Idd > 1.5mA typ).
DD
ON Mode, the device is able to source
FUNCTIONAL DEVICE OPERATION
DD
ON mode
DD
on mode. If the duration
LOW POWER MODES
33904/5
DD
33