mc33905s Freescale Semiconductor, Inc, mc33905s Datasheet - Page 72

• Manufacturer Part Number: mc33905s
• Description: System Basis Chip Gen2 With High Speed Can And Lin Interface
• Manufacturer: Freescale Semiconductor, Inc

72
33904/5
SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
Table 33. INT Register, INT
[b_15 b_14] 10_010 [P/N]
MOSI First byte [15-8]
Bits
Condition for default
b7
b6
b5
b4
b3
b2
b0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
01 10_ 010P
Default state
CAN failure - control bit for CAN failure INT (CANH/L to GND, VDD or VSUP, CAN over-current, Driver Over Temp, TX-PD,
RX-PR, RX2HIGH, and CANBUS Dominate clamp)
INT disable
INT enable.
MCU req - Control bit to request an INT. INT will occur once when the bit is enable
INT disable
INT enable.
not implemented in MC33904
INT disable
INT enable.
not implemented in MC33904
INT disable
INT enable.
I/O - Bit to control I/O interruption: I/O Wake-up
INT disable
INT enable.
SAFE - description to be done
INT disable
INT enable.
Vmon - enable interruption by voltage monitoring of one of the voltage regulator: V
VDD_Temp_prewarning), VSUV, VSOV, VSENSElow, 5V-CAN low or thermal shutdown, V
INT disable
INT enable.
CAN failure
bit 7
0
MCU req
bit 6
0
LIN1 fail
bit 5
0
Description
MOSI Second Byte, bits 7-0
LIN0fail
bit 4
0
POR
bit 3
I/O
0
AUX
Analog Integrated Circuit Device Data
, 5V-CAN, V
SAFE
bit 2
0
AUX
low or V
Freescale Semiconductor
DD
bit 1
(IDD Over-current,
0
-
AUX
over-current
Vmon
bit 0
0