mc33905s Freescale Semiconductor, Inc, mc33905s Datasheet - Page 61

• Manufacturer Part Number: mc33905s
• Description: System Basis Chip Gen2 With High Speed Can And Lin Interface
• Manufacturer: Freescale Semiconductor, Inc

Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 16. Initialization Watchdog Registers, INIT W/D (note: register can be written only in INIT mode)
no W/D + 00
no W/D + 01
no W/D + 10
no W/D + 11 In Low Power V
W/D + 00
W/D + 01
W/D + 10
W/D + 11
[b_15 b_14] 0_0110 [P/N]
b6, b5
b3, b2
MOSI First Byte [15-8]
Bit
Condition for default
b7
b4
00
01
10
11
b1
b0
0
1
0
1
0
1
0
1
01 00 _ 110 P
Default state
MCU_OC, OC-TIM - In Low Power V
In Low Power V
threshold for a time > I_mcu_OC is wake-up event. I_mcu_OC time is selected in Timer register (selection range from 3 to 32ms)
In Low Power V
In Low Power V
DD
DD
In Low Power V
ON Mode, V
INT source read must occur before the remaining of the current W/D period plus 2 complete W/D periods.
ON Mode, V
WD2INT - Select the maximum time delay between INT occurrence and INT source read SPI command
WD2INT
WD Safe - Select the activation of the SAFE terminal low, at first or second consecutive RESET pulse
Watchdog operation is WINDOW, W/D refresh must occur in the open window (second half of period)
bit 7
0
In Low Power V
DD
DD
Vdd disable when Vsup1 is below typ 4V (parameter Vsup-th1), and device in Reset mode
Enhanced 4: Refresh is done using the Random Code, and by four 16 bits command.
Enhanced 2: Refresh is done using the Random Code, and by two 16 bits command.
ON Mode, V
ON Mode, V
Crank - Select the Vsup1 threshold to disable Vdd, while Vsup1 is falling toward gnd
DD
Watchdog operation is TIME OUT, W/D refresh can occur anytime in the period
DD
Enhanced 1: Refresh is done using the Random Code, and by a single 16 bits.
Function disable. No constraint between INT occurrence and INT source read.
DD
current > V
MCU_OC
SAFE terminal is set low at the time of the RESET terminal low activation
current > V
WD N/Win - Select the Watchdog (W/D) Window or Time out operation
DD
Simple Watchdog selection: W/D refresh done by a 8bits or 16 bits SPI
SAFE terminal is set low at the second consecutive time RESET pulse
ON Mode, V
bit 6
1
ON, select watchdog refresh and V
Vdd kept ON when Vsup1 is below typ4V (parameter Vsup_th1)
WD_spi[1] WD_spi[0] - Select the Watchdog (W/D) Operation
In Low Power V
In Low Power V
DD
DD
DD
DD_OC_LP
ON Mode, V
current > V
current > V
DD_OC_LP
In low power mode, when W/D is not selected
DD
device electrical parameters (approx 1.5mA)
OC-TIM
In low power mode when W/D is selected
register (selection range from 3 to 32ms)
current > V
bit 5
0
threshold for a time > I_mcu_OC is a wake-up event. I_mcu_OC time is selected in Timer
DD_OC_LP
DD_OC_LP
threshold for a time < I_mcu_OC is a W/D refresh condition. V
DD
DD
DD
ON Mode, V
ON Mode, V
over-current for a time > 100μs (typ) is a wake-up event.
DD_OC_LP
Description
WD Safe
MOSI Second Byte, bits 7-0
threshold has no effect. W/D refresh must occur by SPI command.
threshold has no effect. W/D refresh must occur by SPI command.
bit 4
DD
DD
threshold for a time > 100μs (typ) is a wakeup event
DD
over-current has no effect
over-current has no effect
current monitoring functionality. V
POR
DETAIL OF CONTROL BITS AND REGISTER MAPPING
WD_spi[1]
bit 3
0
WD_spi[0]
bit 2
0
SERIAL PERIPHERAL INTERFACE
DD_OC_LP
WD N/Win
bit 1
1
DD
threshold is defined in
current > V
Crank
DD_OC_LP
bit 0
0
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