mc33905s Freescale Semiconductor, Inc, mc33905s Datasheet - Page 65

• Manufacturer Part Number: mc33905s
• Description: System Basis Chip Gen2 With High Speed Can And Lin Interface
• Manufacturer: Freescale Semiconductor, Inc

TIMER REGISTERS
Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 20. Timer Register A, Low Power Vdd over current & Watchdog Period Normal mode, TIM_A
Table 21. Timer Register B, Cyclic Sense and Cyclic INT, in Device Low Power Mode, TIM_B
[b_15 b_14] 01_010 [P/N]
MOSI First Byte [15-8]
[b_15 b_14] 01_011 [P/N]
MOSI First Byte [15-8]
Condition for default
Condition for default
01 01_ 010 P
Default state
b7
b3
0
1
0
1
01 01_ 011 P
Default state
b4, b3
00
01
10
11
6 (def)
000
000
3
4
8
000
2.5
3.5
3
4
Cyc-sen[3]
I_mcu[2]
bit 7
bit 7
0
0
001
001
12
16
6
8
001
b7
5
6
7
8
0
1
Watchdog Period in Device Normal Mode
Cyc-sen[2]
I_mcu[1]
bit 6
bit 6
0
0
Low Power Vdd over current
3 (def)
010
010
12
16
24
32
010
00
10
12
14
16
4
Cyc-sen[1]
I_mcu[1]
bit 5
bit 5
Cyclic Interrupt (ms)
0
0
Cyclic sense (ms)
011
011
011
01
20
24
28
32
24
32
48
64
6
8
Cyc-sen[0]
W/D Nor[4]
MOSI Second Byte, bits 7-0
MOSI Second Byte, bits 7-0
bit 4
b2, b1, b0
bit 4
b6, b5, b4
b2, b1, b0
0
1
b6, b5
POR
POR
100
40
48
56
64
100
100
128
10
12
16
48
64
96
DETAIL OF CONTROL BITS AND REGISTER MAPPING
Cyc-int[3]
W/D_N[4]
(ms)
bit 3
bit 3
0
1
(ms)
101
112
128
80
96
101
128
101
192
258
Cyc-int[2]
W/D_Nor[3]
11
24
32
96
bit 2
bit 2
0
1
SERIAL PERIPHERAL INTERFACE
256 (def)
110
160
192
224
Cyc-int[1]
110
192
256
110
384
512
W/D_N[2]
bit 1
bit 1
0
1
111
320
384
448
512
Cyc-int[0]
W/D_Nor[0]
1024
111
384
512
111
768
bit 0
0
bit 0
0
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