lan9312 Standard Microsystems Corp., lan9312 Datasheet - Page 101

• Manufacturer Part Number: lan9312
• Description: Lan9312 High Performance Two Port 10/100 Managed Ethernet Switch With 32-bit Non-pci Cpu Interface
• Manufacturer: Standard Microsystems Corp.

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
8.4
8.4.1
8.4.1.1
8.4.1.2
8.4.2
This section details the characteristics and special restrictions of the various supported host cycles.
For detailed timing specifications on supported PIO read/write operations, refer to
Specifications". The LAN9312 supports the following host cycles:
Read Cycles:
Write Cycles:
Special Situations
Reset Ending During a Read Cycle
If a reset condition terminates during an active read cycle, the tail end of the read cycle will be ignored
by the LAN9312.
Writes Following a Reset
Following any reset, writes from the host bus are ignored until after a read cycle is performed.
Special Restrictions on Back-to Back Write-Read Cycles
It is important to note that there are specific restrictions on the timing of back-to-back host write-read
operations. These restrictions concern reading the host control registers after any write cycle to the
LAN9312. In some cases there is a delay between writing to the LAN9312, and the subsequent side
effect (change in the control register value). For example, when writing to the TX Data FIFO, it takes
up to 135ns for the level indication to change in the
In order to prevent the host from reading stale data after a write operation, minimum wait periods have
been established. These periods are specified in
specified period of time after any write to the LAN9312 before reading the resource specified in the
table. These wait periods are for read operations that immediately follow any write cycle. Note that the
required wait period is dependant upon the register being read after the write.
Performing “dummy” reads of the
to guarantee that the minimum write-to-read timing restriction is met.
dummy reads that are required before reading the register indicated. The number of BYTE_TEST
reads in this table is based on the minimum timing for T
busses the number of reads may be reduced as long as the total time is equal to, or greater than the
time specified in the table. Note that dummy reads of the BYTE_TEST register are not required as
long as the minimum time period is met.
Host Interface Timing
REGISTER NAME
PIO Reads
PIO Burst Reads
RX Data FIFO Direct PIO Reads
RX Data FIFO Direct PIO Burst Reads
PIO Writes
TX Data FIFO Direct PIO Writes
RX Data FIFO
(nCS or nWR controlled)
(nCS or nRD controlled)
(nCS or nRD controlled)
Table 8.1 Read After Write Timing Rules
Byte Order Test Register (BYTE_TEST)
DATASHEET
(nCS or nWR controlled)
(nCS or nRD controlled)
MINIMUM WAIT TIME FOR
READ FOLLOWING ANY
WRITE CYCLE (IN NS)
101
(nCS or nRD controlled)
Table
0
TX FIFO Information Register
8.1. The host processor is required to wait the
cyc
(45ns). For microprocessors with slower
Table 8.1
(ASSUMING T
NUMBER OF BYTE_TEST
register is a convenient way
shows the number of
Revision 1.2 (04-08-08)
READS
(TX_FIFO_INF).
Section 15.5, "AC
0
CYC
OF 45NS)