lan9312 Standard Microsystems Corp., lan9312 Datasheet - Page 37

• Manufacturer Part Number: lan9312
• Description: Lan9312 High Performance Two Port 10/100 Managed Ethernet Switch With 32-bit Non-pci Cpu Interface
• Manufacturer: Standard Microsystems Corp.

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
4.2.1
4.2.1.1
RESET SOURCE
Digital Reset
Virtual PHY
Port 2 PHY
Port 1 PHY
Soft Reset
nRST Pin
Note 4.1
Chip-Level Resets
A chip-level reset event activates all internal resets, effectively resetting the entire LAN9312.
Configuration straps are latched, and the EEPROM Loader is run as a result of chip-level resets. A
chip-level reset is initiated by assertion of any of the following input events:
Chip-level reset completion/configuration can be determined by polling the READY bit of the
Configuration Register (HW_CFG)
When set, the READY bit indicates that the reset has completed and the device is ready to be
accessed.
With the exception of the
Register
(RESET_CTL), read access to any internal resources is forbidden while the READY bit is cleared.
Writes to any address are invalid until the READY bit is set.
Note: The LAN9312 must be read at least once after any chip-level reset to ensure that write
Power-On Reset (POR)
A power-on reset occurs whenever power is initially applied to the LAN9312, or if the power is removed
and reapplied to the LAN9312. This event resets all circuitry within the device. Configuration straps
are latched, and the EEPROM Loader is run as a result of this reset.
Power-On Reset (POR)
nRST Pin Reset
POR
operations function properly.
(PMT_CTRL),
In the case of a soft reset, the EEPROM Loader is run, but loads only the MAC address
into the Host MAC. No other values are loaded by the EEPROM Loader in this case.
X
X
X
Table 4.1 Reset Sources and Affected LAN9312 Circuitry
X
X
X
Byte Order Test Register
Hardware Configuration Register
X
X
X
or
DATASHEET
X
X
X
X
X
Power Management Control Register (PMT_CTRL)
37
X
X
X
X
X
X
X
X
(BYTE_TEST), and
(HW_CFG),
X
X
X
X
X
X
Power Management Control
Reset Control Register
X
X
X
Revision 1.2 (04-08-08)
X
X
until it is set.
Note 4.1
Hardware
X
X
X