lan9312 Standard Microsystems Corp., lan9312 Datasheet - Page 451
lan9312
Manufacturer Part Number
lan9312
Description
Lan9312 High Performance Two Port 10/100 Managed Ethernet Switch With 32-bit Non-pci Cpu Interface
Manufacturer
Standard Microsystems Corp.
Datasheet
1.LAN9312.pdf
(458 pages)
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High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9312
15.5.8
SYMBOL
t
cycle
t
t
t
A[x:2], END_SEL
t
t
t
asu
dsu
csh
csl
ah
dh
nCS, nWR
PIO Write Cycle Timing
Please refer to
Note: A PIO write cycle begins when both nCS and nWR are asserted. The cycle ends when either
Write Cycle Time
nCS, nWR Assertion Time
nCS, nWR De-assertion Time
Address Setup to nCS, nWR Assertion
Address Hold Time
Data Setup to nCS, nWR De-assertion
Data Hold Time
D[31:0]
or both nCS and nWR are de-asserted. These signals may be asserted and de-asserted in any
order.
Section 8.4.8, "PIO Writes," on page 110
Table 15.12 PIO Write Cycle Timing Values
DESCRIPTION
Figure 15.8 PIO Write Cycle Timing
t
asu
DATASHEET
451
t
csl
t
t
for a functional description of this mode.
cycle
dsu
MIN
45
32
13
0
0
7
0
t
dh
t
ah
TYP
t
csh
Revision 1.2 (04-08-08)
MAX
UNITS
nS
nS
nS
nS
nS
nS
nS
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