tda5225 Infineon Technologies Corporation, tda5225 Datasheet - Page 112

• Manufacturer Part Number: tda5225
• Description: Enhanced Sensitivity Multi-channel Quad-conf Igurat Ion Receiver With Digital Slicer
• Manufacturer: Infineon Technologies Corporation

Table 1
Register Short Name
B_PLLFRAC0C2
B_PLLFRAC1C2
B_PLLFRAC2C2
B_PLLINTC3
B_PLLFRAC0C3
B_PLLFRAC1C3
B_PLLFRAC2C3
C_IF1
C_WURSSITH1
C_WURSSIBL1
C_WURSSIBH1
C_WURSSITH2
C_WURSSIBL2
C_WURSSIBH2
C_WURSSITH3
C_WURSSIBL3
C_WURSSIBH3
C_WULOT
C_AFCLIMIT
C_AFCAGCD
C_AFCSFCFG
C_AFCK1CFG0
C_AFCK1CFG1
C_AFCK2CFG0
C_AFCK2CFG1
C_PMFUDSF
C_AGCSFCFG
C_AGCCFG0
C_AGCCFG1
C_AGCTHR
C_DIGRXC
C_ISUPFCSEL
C_PDECF
C_PDECSCFSK
Data Sheet
Register Overview (cont’d)
Register Long Name
PLL Fractional Division Ratio Register 0 Channel 2 15E
PLL Fractional Division Ratio Register 1 Channel 2 15F
PLL Fractional Division Ratio Register 2 Channel 2 160
PLL MMD Integer Value Register Channel 3
PLL Fractional Division Ratio Register 0 Channel 3 162
PLL Fractional Division Ratio Register 1 Channel 3 163
PLL Fractional Division Ratio Register 2 Channel 3 164
RSSI Wake-Up Threshold for Channel 1 Register 21B
RSSI Wake-Up Blocking Level Low Channel 1
Register
RSSI Wake-Up Blocking Level High Channel 1
Register
RSSI Wake-Up Threshold for Channel 2 Register 21E
RSSI Wake-Up Blocking Level Low Channel 2
Register
RSSI Wake-Up Blocking Level High Channel 2
Register
RSSI Wake-Up Threshold for Channel 3 Register 221
RSSI Wake-Up Blocking Level Low Channel 3
Register
RSSI Wake-Up Blocking Level High Channel 3
Register
Wake-Up on Level Observation Time Register
AFC Limit Configuration Register
AFC/AGC Freeze Delay Register
AFC Start/Freeze Configuration Register
AFC Integrator 1 Gain Register 0
AFC Integrator 1 Gain Register 1
AFC Integrator 2 Gain Register 0
AFC Integrator 2 Gain Register 1
Peak Memory Filter Up-Down Factor Register
AGC Start/Freeze Configuration Register
AGC Configuration Register 0
AGC Configuration Register 1
AGC Threshold Register
Image Supression Fc Selection Register
Pre Decimation Factor Register
Pre Decimation Scaling Register FSK Mode
IF1 Register
Digital Receiver Configuration Register
112
Offset Address
161
216
21C
21D
21F
220
222
223
225
22A
22B
22C
22D
22E
22F
230
231
232
233
234
235
236
238
239
23A
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Register Overview
V1.0, 2010-02-19
Page Number
Appendix
TDA5225