tda5225 Infineon Technologies Corporation, tda5225 Datasheet - Page 76

• Manufacturer Part Number: tda5225
• Description: Enhanced Sensitivity Multi-channel Quad-conf Igurat Ion Receiver With Digital Slicer
• Manufacturer: Infineon Technologies Corporation

2.8
2.8.1
An SPI instruction allows a maximum address space of 8 bit. The address space for
supporting more than one configuration set is exceeding this 8 bit address room.
Therefore a page switch is introduced, which can be applied via register SFRPAGE (see
Figure
Figure 52
2.8.2
The register list is attached in the Appendix at the end of the document.
Registers for Configurations B, C and D are equivalent and not shown in detail.
All registers with prefix “A_” are related to Configuration A. All these registers are also
available for Configuration B, C and D having the prefix “B_”, “C_” and “D_”.
Data Sheet
52).
Digital Control (SFR Registers)
SFR Address Paging
SFR Register List and Detailed SFR Description
SFR Address Paging
0x000
0x080
0x0FF
0x100
0x180
0x1FF
0x200
0x280
0x2FF
0x300
0x380
0x3FF
1)
2), 4)
3)
Configuration dependent register block (4 protocol specific sets)
Configuration independent registers (common for all configurations )
Reserved – Forbidden area
page switch via SFRPAGE register
map (“mirror“ ) to the same physical address space
Configuration A
Configuration B
Configuration C
Configuration D
logical address space
Common Registers
Common Registers
Common Registers
Common Registers
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1)
1)
1)
1)
2)
4)
2)
4)
2)
4)
2)
4)
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3)
3)
3)
3)
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1023
128
255
256
384
511
512
640
767
768
896
0
d
d
d
d
d
d
d
d
d
d
d
d
Configuration A
Configuration B
Configuration C
Configuration D
physical address space
Common Registers
Reserved
Reserved
Reserved
Reserved
Reserved
Functional Description
1)
1)
1)
1)
2)
4)
2)
2)
2)
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V1.0, 2010-02-19
TDA5225