tda5225 Infineon Technologies Corporation, tda5225 Datasheet - Page 67

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tda5225

Manufacturer Part Number
tda5225
Description
Enhanced Sensitivity Multi-channel Quad-conf Igurat Ion Receiver With Digital Slicer
Manufacturer
Infineon Technologies Corporation
Datasheet

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TDA5225
Functional Description
2.6.2
Polling Timer Unit
SPM
SPM
SPM
f
/ 64
f
f
sys
RT
OnOff
Reference-Timer
On-Off-Timer
Active-Idle Period Timer
(8 Bit)
(14 Bit)
(5 / 8 Bit)
Self-Polling-Mode (SPM)
No WU
FSM
Polling Mode
to
Master-Control-Unit
Figure 44
Polling Timer Unit
The Polling Timer Unit consists of a Counter Stage and a Control FSM (Finite State
Machine).
The Counter Stage is divided into three sub-modules.
The Reference Timer is used to divide the state machine clock (f
/64) into the slower
sys
clock required for the SPM timers.
The On-Off Timer and the Active Idle Period Timer are used to generate the polling
signal. The entire unit is controlled by the SPM FSM.
The TDA5225 is able to handle up to four different sets of configurations automatically.
However, the example and figure in this subsection only show up to two configuration
sets for the sake of clarity.
Data Sheet
67
V1.0, 2010-02-19

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