tda5225 Infineon Technologies Corporation, tda5225 Datasheet - Page 72

• Manufacturer Part Number: tda5225
• Description: Enhanced Sensitivity Multi-channel Quad-conf Igurat Ion Receiver With Digital Slicer
• Manufacturer: Infineon Technologies Corporation

2.7
2.7.1
The definition for the bit rate in the following description is:
If a symbol contains n chips (for Manchester n=2; for NRZ n=1) the chip rate is n times
the bit rate:
2.7.2
Several different definitions for the Manchester duty cycle (MDC) are in place. To avoid
wrong interpretation some of the definitions are given below.
Figure 48
This definition determinates the duty cycle to be the ratio of the high pulse width and the
ideal symbol period. The DC content is constant and directly proportional to the specified
duty cycle.
For ΔT > 0 the high period is longer than the chip-period and for ΔT < 0 the high period
is shorter than the chip-period.
Data Sheet
Definitions
Definition of Bit Rate
Definition of Manchester Duty Cycle
Definition A: Level-based definition
1. chip
Δ T
bit = 1
1
ΔT
2. chip
T
H
T
H
T
T
T
1
1
MDC = Duration of H-level / Symbol period
b it
b it
b it
chiprate
bitrate
Level-based Definition
MDC < 50%
=
MDC > 50%
=
72
0
0
symbols
--------------------- -
n
×
s
bitrate
T
T
0
0
b it
b it
T
H
T
H
Functional Description
1
1
V1.0, 2010-02-19
TDA5225