tda5225 Infineon Technologies Corporation, tda5225 Datasheet - Page 116

• Manufacturer Part Number: tda5225
• Description: Enhanced Sensitivity Multi-channel Quad-conf Igurat Ion Receiver With Digital Slicer
• Manufacturer: Infineon Technologies Corporation

Table 2
Register Short Name
A_PLLINTC3
A_PLLFRAC0C3
A_PLLFRAC1C3
A_PLLFRAC2C3
SFRPAGE
PPCFG0
PPCFG1
PPCFG2
RXRUNCFG0
RXRUNCFG1
CLKOUT0
CLKOUT1
CLKOUT2
RFC
BPFCALCFG0
BPFCALCFG1
XTALCAL0
XTALCAL1
RSSIMONC
ADCINSEL
RSSIOFFS
RSSISLOPE
IM0
IM1
SPMAP
SPMIP
SPMC
SPMRT
SPMOFFT0
SPMOFFT1
SPMONTA0
SPMONTA1
SPMONTB0
SPMONTB1
SPMONTC0
SPMONTC1
SPMONTD0
SPMONTD1
Data Sheet
Register Overview and Reset Value (cont’d)
Register Long Name
PLL MMD Integer Value Register Channel 3
PLL Fractional Division Ratio Register 0 Channel 3 062
PLL Fractional Division Ratio Register 1 Channel 3 063
PLL Fractional Division Ratio Register 2 Channel 3 064
Special Function Register Page Register
PP0 and PP1 Configuration Register
PP2 and PP3 Configuration Register
PPx Port Configuration Register
RX RUN Configuration Register 0
RX RUN Configuration Register 1
Clock Divider Register 0
Clock Divider Register 1
Clock Divider Register 2
RF Control Register
BPF Calibration Configuration Register 0
BPF Calibration Configuration Register 1
XTAL Coarse Calibration Register
XTAL Fine Calibration Register
RSSI Monitor Configuration Register
ADC Input Selection Register
RSSI Offset Register
RSSI Slope Register
Interrupt Mask Register 0
Interrupt Mask Register 1
Self Polling Mode Active Periods Register
Self Polling Mode Idle Periods Register
Self Polling Mode Control Register
Self Polling Mode Reference Timer Register
Self Polling Mode Off Time Register 0
Self Polling Mode Off Time Register 1
Self Polling Mode On Time Config A Register 0
Self Polling Mode On Time Config A Register 1
Self Polling Mode On Time Config B Register 0
Self Polling Mode On Time Config B Register 1
Self Polling Mode On Time Config C Register 0
Self Polling Mode On Time Config C Register 1
Self Polling Mode On Time Config D Register 0
Self Polling Mode On Time Config D Register 1
116
Offset Address
061
080
081
082
083
084
085
086
087
088
089
08A
08B
08C
08D
08E
08F
090
091
094
095
096
097
098
099
09A
09B
09C
09D
09E
09F
0A0
0A1
0A2
0A3
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Register Overview
V1.0, 2010-02-19
Reset Value
13
F3
07
09
00
50
12
00
FF
FF
0B
00
00
07
07
04
10
00
01
00
80
80
00
00
01
01
00
01
01
00
01
00
01
00
01
00
01
00
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
Appendix
TDA5225