tda5225 Infineon Technologies Corporation, tda5225 Datasheet - Page 53

• Manufacturer Part Number: tda5225
• Description: Enhanced Sensitivity Multi-channel Quad-conf Igurat Ion Receiver With Digital Slicer
• Manufacturer: Infineon Technologies Corporation

registers are updated at every write instruction, so only the last transmission can be
checked by a read out of these two registers.
Figure 30
To write to the device in Burst mode, the SPI master has to select the SPI slave unit
first. Therefore the master has to drive the NCS line to low. After the instruction byte and
the start address byte have been transferred to the SPI slave (MSB first) the successive
data bytes will be stored into the automatically addressed registers.
To verify the SPI Burst Write transfer, the current address (start address, start address
+ 1, etc.) is stored in register SPIAT and the current data field of the frame is stored in
register SPIDT. At the end of the Burst Write frame the latest address as well as the
latest data field can be read out to verify the transfer. Note that some error in one of the
intermediate data bytes can not be detected by reading SPIDT.
Driving the NCS line to high will end the Burst frame.
A single SPI Burst Write command can be applied very efficiently for data transfer either
within a register block of configuration dependent registers or within the block of
configuration independent registers.
Figure 31
Data Sheet
NCS
SCK
SDO
NCS
SCK
SDO
SDI
SDI
high impedance Z
high impedance Z
I7 I6
1
I7 I6
1
I5 I4
Instruction
I5 I4
Instruction
I3 I2 I1 I0
Write Register
Burst Write Registers
I3 I2 I1 I0
8
A7 A6
1
8
A7 A6
Register Address
A5 A4
1
Frame
Register Start Address
A3 A2 A1 A0
A5 A4
A3 A2 A1 A0
8
D7 D6 D5 D4
1
8
Data Byte
D7 D6 D5 D4
1
D3 D2
Data Byte (i)
D1 D0
8
D3 D2
53
D1 D0
I7 I6
8
1
D7 D6
1
I5 I4
Instruction
D5 D4
Data Byte (i+1)
I3 I2 I1 I0
D3 D2 D1 D0
8
A7 A6
1
8
Functional Description
Register Address
A5 A4
Frame
A3 A2 A1 A0
D7 D6 D5 D4
1
8
V1.0, 2010-02-19
D7 D6 D5 D4
1
Data Byte (i+x)
TDA5225
Data Byte
D3 D2
D3 D2
D1 D0
D1 D0
8
8