74act1284msax-nl Fairchild Semiconductor, 74act1284msax-nl Datasheet

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74act1284msax-nl

Manufacturer Part Number
74act1284msax-nl
Description
74act1284 Ieee 1284 Transceiver
Manufacturer
Fairchild Semiconductor
Datasheet
© 2000 Fairchild Semiconductor Corporation
74ACT1284SC
74ACT1284MSA
74ACT1284MTC
74ACT1284
IEEE 1284 Transceiver
General Description
The 74ACT1284 contains four non-inverting bidirectional
buffers and three non-inverting buffers with open Drain out-
puts and high drive capability on the B Ports. It is intended
to provide a standard signaling method for a bi-direction
parallel peripheral in an Extended Capabilities Port mode
(ECP).
The HD (active HIGH) input pin enables the B Ports to
switch from open Drain to a high drive totem pole output,
capable of sourcing 14 mA on all seven buffers. The DIR
input determines the direction of data flow on the bidirec-
tional buffers. DIR (active HIGH) enables data flow from
A Ports to B Ports. DIR (active LOW) enables data flow
from B Ports to A Ports.
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
FACT
Order Number
HD
DIR
A
B
A
B
1
1
5
5
Pin Names
- A
- B
- A
- B
is a trademark of Fairchild Semiconductor Corporation.
4
4
7
7
Package Number
High Drive Enable input (Active HIGH)
Direction Control Input
Side A Inputs or Outputs
Side B Inputs or Outputs
Side A Inputs
Side B Outputs
MSA20
MTC20
M20B
Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
DS011683
Features
Connection Diagram
TTL-compatible inputs
A Ports have standard 4 mA totem pole outputs
Typical input hysteresis of 0.5V
B Port high drive source/sink capability of 14 mA
Bidirectional non-inverting buffers
Supports IEEE P1284 Level 1 and Level 2 signaling
standards for bidirectional parallel communications
between personal computers and printing peripherals
B Port outputs in High Impedance mode during power
down
Guaranteed 4000V minimum ESD protection
Package Description
June 1996
Revised November 2000
www.fairchildsemi.com

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74act1284msax-nl Summary of contents

Page 1

... Side B Outputs 5 7 FACT is a trademark of Fairchild Semiconductor Corporation. © 2000 Fairchild Semiconductor Corporation Features TTL-compatible inputs A Ports have standard 4 mA totem pole outputs Typical input hysteresis of 0.5V B Port high drive source/sink capability Bidirectional non-inverting buffers Supports IEEE P1284 Level 1 and Level 2 signaling ...

Page 2

Truth Table Inputs DIR Note Open Drain Outputs 5 7 Note Open Drain Outputs 1 7 Logic Diagram www.fairchildsemi.com Outputs Data to A ...

Page 3

Absolute Maximum Ratings (Note 4) Supply Voltage ( Input Diode Current ( 0. 0. Input Voltage ( Side 0. Input Voltage (V ...

Page 4

AC Electrical Characteristics Symbol Parameter PHL PLH PHL ...

Page 5

AC Loading and Waveforms FIGURE 1. Port Propagation Delay Waveforms FIGURE 2. B Output Test Load and Waveforms FIGURE Direction Test Load and Waveforms for Outputs A FIGURE Direction ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M20B Package Number MSA20 6 ...

Page 7

Physical Dimensions Physical Dimensions inches (millimeters) unless otherwise noted (Continued) inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no ...

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