dm74as169a Fairchild Semiconductor, dm74as169a Datasheet

dm74as169a

Manufacturer Part Number

dm74as169a

Description

Synchronous 4-bit Binary Up/down Counter

Manufacturer

Fairchild Semiconductor

Datasheet

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DM74AS169AM

DM74AS169AN

DM74AS169A

Synchronous 4-Bit Binary Up/Down Counter

General Description

These synchronous presettable counters feature an inter-

nal carry look ahead for cascading in high speed counting

applications. The DM74AS169 is a 4-bit binary up/down

counter. The carry output is decoded to prevent spikes dur-

ing normal mode of counting operation. Synchronous oper-

ation is provided so that outputs change coincident with

each other when so instructed by count enable inputs and

internal gating. This mode of operation eliminates the out-

put counting spikes which are normally associated with

asynchronous (ripple clock) counters. A buffered clock

input triggers the four flip-flops on the rising (positive going)

edge of clock input waveform.

These counters are fully programmable; that is, the outputs

may each be preset either HIGH or LOW. The load input

circuitry allows loading with carry-enable output of cas-

caded counters. As loading is synchronous, setting up a

LOW level at the load input disables the counter and

causes the outputs to agree with the data inputs after the

next clock pulse.

The carry look-ahead circuitry permits cascading counters

for n-bit synchronous applications without additional gating.

Both count enable inputs (P and T) must be LOW to count.

The direction of the count is determined by the level of the

up/down input. When the input is HIGH, the counter counts

UP; when LOW, it counts DOWN. Input T is fed forward to

enable the carry outputs. The carry output thus enabled will

produce a LOW level output pulse with a duration approxi-

mately equal to the HIGH portion of the QA output when

counting UP, and approximately equal to the LOW portion

of the QA output when counting DOWN. This LOW level

overflow carry pulse can be used to enable successively

cascaded stages. Transitions at the enable P or T inputs

are allowed regardless of the level of the clock input.

The control functions for these counters are fully synchro-

nous. Changes at control inputs (enable P, enable T, load,

up/down) which modify the operating mode have no effect

until clocking occurs. The function of the counter (whether

enabled, disabled, loading or counting) will be dictated

solely by the conditions meeting the stable setup and hold

times.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Order Number

Package Number

M16A

N16E

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

DS006292

Features

Switching Specifications at 50 pF

Switching Specifications guaranteed over full tempera-

ture and V

Advanced oxide-isolated, ion-implanted Schottky TTL

process

Functionally and pin-for-pin compatible with Schottky

and low power Schottky TTL counterpart

Improved AC performance over Schottky and low power

Schottky counterparts

Synchronously programmable

Internal look ahead for fast counting

Carry output for n-bit cascading

Synchronous counting

Load control line

ESD inputs

Package Description

range

April 1984

Revised March 2000

www.fairchildsemi.com

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dm74as169a Summary of contents

Page 1

... Package Number DM74AS169AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74AS169AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. ...

Page 2

... Connection Diagram Logic Diagram www.fairchildsemi.com DM74AS169A 2 ...

Page 3

Absolute Maximum Ratings Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Typical JA N Package M Package Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input ...

Page 4

Switching Characteristics over recommended operating free air temperature range Symbol Parameter f Maximum Clock Frequency MAX t Propagation Delay Time PLH LOW-to-HIGH Level Output t Propagation Delay Time PHL HIGH-to-LOW Level Output t Propagation Delay Time PLH LOW-to-HIGH Level Output ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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