psd813f3 STMicroelectronics, psd813f3 Datasheet - Page 36

• Manufacturer Part Number: psd813f3
• Description: Flash In-system Programmable Isp Peripherals For 8-bit Mcus
• Manufacturer: STMicroelectronics

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Complex PLD (CPLD)
The CPLD can be used to implement system logic
functions, such as loadable counters and shift reg-
isters, system mailboxes, handshaking protocols,
state machines, and random logic. The CPLD can
also be used to generate three External Chip Se-
lect (ECS0-ECS2), routed to Port D.
Although External Chip Select (ECS0-ECS2) can
be produced by any Output Macrocell (OMC),
these three External Chip Select (ECS0-ECS2) on
Port D do not consume any Output Macrocells
(OMC).
As shown in
the following blocks:
Figure 15. Macrocell and I/O Port
36/110
24 Input Macrocells (IMC)
16 Output Macrocells (OMC)
Macrocell Allocator
Figure 13., page
PRODUCT TERMS
MACROCELLS
FROM OTHER
PRODUCT TERM
PT
CLOCK
PT CLEAR
GLOBAL
CLOCK
CLOCK
SELECT
ALLOCATOR
PRODUCT TERMS
PT INPUT LATCH GATE/CLOCK
CPLD MACROCELLS
UP TO 10
POLARITY
SELECT
MACROCELL FEEDBACK
PT OUTPUT ENABLE ( OE )
I/O PORT INPUT
PT PRESET
34, the CPLD has
PR DI LD
D/T
CK
D/T/JK FF
SELECT
MCU DATA IN
CL
Q
MCU LOAD
MCU ADDRESS / DATA BUS
SELECT
COMB.
/REG
MACROCELL
CONTROL
OUT TO
DATA
LOAD
MACROCELL
MCU
I/O PORT
ALLOC.
TO
Each of the blocks are described in the sections
that follow.
The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the PSD internal data bus
and can be directly accessed by the MCU. This
enables the MCU software to load data into the
Output Macrocells (OMC) or read data from both
the Input and Output Macrocells (IMC and OMC).
This feature allows efficient implementation of sys-
tem logic and eliminates the need to connect the
data bus to the AND Array as required in most
standard PLD macrocell architectures.
OUTPUT
CPLD
Product Term Allocator
AND Array capable of generating up to 137
product terms
Four I/O Ports.
ALE/AS
DATA
CPLD OUTPUT
ADDRESS OUT
I/O PORTS
WR
INPUT MACROCELLS
WR
LATCHED
PDR
D
TO OTHER I/O PORTS
D
REG.
DIR
INPUT
Q
Q
MUX
SELECT
Q
Q D
D
G
I/O PIN
AI02874