psd813f3 STMicroelectronics, psd813f3 Datasheet - Page 84
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psd813f3
Manufacturer Part Number
psd813f3
Description
Flash In-system Programmable Isp Peripherals For 8-bit Mcus
Manufacturer
STMicroelectronics
Datasheet
1.PSD813F3.pdf
(110 pages)
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PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
Table 51. CPLD Macrocell Asynchronous Clock Mode Timing (5V devices)
84/110
f
t
t
t
t
t
t
t
Symbol
MAXA
SA
HA
CHA
CLA
COA
ARDA
MINA
Maximum
Frequency
External
Feedback
Maximum
Frequency
Internal
Feedback
(f
Maximum
Frequency
Pipelined
Data
Input Setup
Time
Input Hold
Time
Clock Input
High Time
Clock Input
Low Time
Clock to
Output Delay
CPLD Array
Delay
Minimum
Clock Period
CNTA
Parameter
)
1/(t
Any macrocell
1/(t
1/(t
Conditions
SA
1/f
CHA
SA
+t
CNTA
+t
COA
+t
COA
CLA
–10)
)
)
Min
16
7
8
9
9
-70
Max
38.4
62.5
71.4
21
11
Min
12
12
12
28
8
-90
26.32
35.71
41.67
Max
30
16
Min
12
14
15
15
39
-15
21.27
27.78
35.71
Max
37
22
Aloc
+ 2
+ 2
PT
Turbo
+ 10
+ 10
+ 10
+ 10
Off
Slew
Rate
– 2
MHz
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns