psd813f3 STMicroelectronics, psd813f3 Datasheet - Page 81
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psd813f3
Manufacturer Part Number
psd813f3
Description
Flash In-system Programmable Isp Peripherals For 8-bit Mcus
Manufacturer
STMicroelectronics
Datasheet
1.PSD813F3.pdf
(110 pages)
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Figure 41. Synchronous Clock Mode Timing – PLD
Table 49. CPLD Macrocell Synchronous Clock Mode Timing (5V devices)
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD0. Decrement times by given amount.
f
t
t
t
t
t
t
t
Symbol
MAX
S
H
CH
CL
CO
ARD
MIN
2. CLKIN (PD1) t
Maximum
Frequency
External
Feedback
Maximum
Frequency
Internal
Feedback
(f
Maximum
Frequency
Pipelined Data
Input Setup
Time
Input Hold Time
Clock High Time
Clock Low Time
Clock to Output
Delay
CPLD Array
Delay
Minimum Clock
Period
CNT
Parameter
)
2
CLCL
REGISTERED
= t
OUTPUT
CLKIN
CH
INPUT
+ t
Any macrocell
1/(t
Conditions
Clock Input
Clock Input
Clock Input
1/(t
CL
1/(t
t
S
.
CH
+t
CH
S
+t
+t
CO
+t
CO
CL
–10)
CL
PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2
)
)
t CH
Min
12
12
0
6
6
-70
Max
40.0
66.6
83.3
13
11
Min
15
10
10
20
0
t CL
-90
30.30
43.48
50.00
Max
t S
18
16
t H
Min
20
15
15
30
0
t CO
-15
25.00
31.25
35.71
Max
22
22
Aloc
Fast
AI02860
+ 2
+ 2
PT
Turbo
+ 10
Off
Slew
rate
– 2
1
81/110
MHz
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns