tc58512ft TOSHIBA Semiconductor CORPORATION, tc58512ft Datasheet - Page 21

• Manufacturer Part Number: tc58512ft
• Description: Tentative Toshiba Mos Digital Integrated Circuit Silicon Gate Cmos
• Manufacturer: TOSHIBA Semiconductor CORPORATION

131072 pages
4096 blocks
Schematic Cell Layout and Address Assignment
Table 1. Addressing
First cycle
Second cycle
Third cycle
Fourth cycle
* : A8 is automatically set to Low or High by a 00H command or a 01H command.
* : l/O2 to l/O8 must be set to Low in the fourth cycle.
Operation Mode: Logic and Command Tables
command operations shown in Table 3. Address input, command input and data input/output are controlled by
the CLE, ALE, CE , WE , RE and WP signals, as shown in Table 2.
Table 2. Logic Table
Command Input
Data Input
Address Input
Serial Data Output
During Programming (Busy)
During Erasing (Busy)
Program, Erase Inhibit
H: V
The Program operation works on page units while the Erase operation works on block units.
The operation modes such as Program, Erase, Read and Reset are controlled by the fourteen different
IH
, L: V
IL
, *: V
IH
Figure 2. Schematic Cell Layout
512
or V
528
I/O8
A16
A24
IL
A7
*L
16
I/O7
A15
A23
A6
*L
I/O6
A14
A22
A5
*L
8I/O
I/O8
32 pages
1 block
I/O5
A13
A21
CLE
A4
*L
H
L
L
L
*
*
*
I/O1
I/O4
A12
A20
A3
*L
A page consists of 528 bytes in which 512 bytes are used for
main memory storage and 16 bytes are for redundancy or for
other uses.
Capacity = 528 bytes ´ 32 pages ´ 4096 blocks
clock cycles, as shown in Table 1.
An address is read in via the I/O port over four consecutive
1 page = 528 bytes
1 block = 528 bytes ´ 32 pages = (16K + 512) bytes
ALE
I/O3
A11
A19
H
A2
L
L
L
*L
*
*
*
I/O2
A10
A18
A1
*L
CE
L
L
L
L
*
*
*
I/O1
A17
A25
A0
A9
A0 to A7
A9 to A25 : Page address
A14 to A25 : Block address
A9 to A13 : NAND address in block
WE
H
*
*
*
: Column address
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RE
H
H
H
*
*
*
TC58512FT
WP
H
H
L
*
*
*
*