tmp89cm42 TOSHIBA Semiconductor CORPORATION, tmp89cm42 Datasheet - Page 200

• Manufacturer Part Number: tmp89cm42
• Description: 8 Bit Microcontroller Tlcs-870/c1 Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

14.4
Functions
RA005
T001CR<T00RUN>
T00MOD<TFF0>
Source clock
Counter
Write to T00PWM
Double buffer
T00PWM
<PWMAD>
T00PWM
<PWMDUTY>
PWM0 pin output
INTTC00 interrupt
request
is "1", the PWM0 pin changes from the "L" to "H" level. If the 2 × n-th overflow occurs at this time, an
INTTC00 interrupt request is generated. (No interrupt request is generated at the 2 × n-th -1 overflow.)
Subsequently, the up counter continues counting up.
to "0x00". The PWM0 pin returns to the level selected at T00MOD<TFF0>.
(Example) Operate TC00 in the 8-bit PWM mode with the operation clock of fcgck/2 and output a duty pulse nearly
When T001CR<T00RUN> is set to "0" during the timer operation, the up counter is stopped and cleared
Becomes the level selected at
TFF0 while the timer is stopped
Write m
equivalent to 11.6 μs (fcgck = 10 MHz)
(Actually, output a total duty pulse of 23.2 μs in 2 cycles (51.2 μs))
m
m
Timer start
(Duty pulse)
Figure 14-6 8-bit PWM Mode Timing Chart
SET
SET
LD
DI
SET
EI
LD
LD
SET
0
m
1
128 counts
(Cycle 1)
When the double buffer is enabled (T00MOD<DBE0>=”1”)
Match detection
m
Write r
(P7FC).0
(P7CR).0
(POFFCR0),0x10
(EIRH).4
(T00MOD),0xF2
(T00PWM),0x74
(T001CR).0
m+1
r
(Duty pulse)
Overflow
128
Counter
clear
No interrupt request
is generated
0
m
128 counts
1
(Cycle 2)
Page 186
Match detection
m
m+1
(Duty pulse)
; Sets P7FC0 to "1"
; Sets P7CR0 to "1"
; Sets TC001EN to "1"
; Sets the interrupt master enable flag to "disable"
; Sets the INTTC00 interrupt enable register to "1"
; Sets the interrupt master enable flag to "enable"
; Selects the 8-bit PWM mode and fcgck/2
; Sets the timer register (duty pulse)
; (11.6μs × 2) / (2/fcgck) = 0x74
; Starts TC00
128
Overflow
Counter
clear
Reflected by an
interrupt request
Interrupt request
0
r
r
1
128 counts
(Cycle 3)
Write s
s
Match detection
r
r+1
Overflow
128
(Duty pulse)
Counter
clear
No interrupt request
is generated
0
128 counts
1
r+1
(Cycle 4)
Additional pulse
Match detection
r
Timer stop
r+1
TMP89CM42
128
s
Counter
clear
Reflected by an
interrupt request
Returns to the
level selected
at TFF0
0
1
0