tmp89cm42 TOSHIBA Semiconductor CORPORATION, tmp89cm42 Datasheet - Page 205

• Manufacturer Part Number: tmp89cm42
• Description: 8 Bit Microcontroller Tlcs-870/c1 Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

RA005
T001CR<T00RUN>
T00MOD<TFF0>
Source clock
Counter
Write to T00PWM
Double buffer
T00PWM
Write to T00REG
Double buffer
T00REG
PPG0 pin output
INTTC00 interrupt
request
(Example) Operate TC00 in the 8-bit PPG mode with the operation clock of fcgck/2 and output the 8μs duty pulse in
Becomes the level selected at
TFF0 while the timer is stopped
Write m
Write p
32μs cycles (fcgck = 10 MHz)
m
m
p
p
Timer start
SET
SET
LD
DI
SET
EI
LD
LD
LD
SET
(Duty pulse)
Figure 14-9 8-bit PPG Mode Timing Chart
0
m
1
(1 cycle)
When the double buffer is enabled (T00MOD<DBE0>=”1”)
p
Match detection
Match detection
m
Write r
(P7FC).0
(P7CR).0
(POFFCR0),0x10
(EIRH).4
(T00MOD),0xF3
(T00REG),0xA0
(T00PWM),0x28
(T001CR).0
m+1
r
Write s
s
(Duty pulse)
p
Counter
clear
s
r
0
r
1
(1 cycle)
Page 191
s
Match detection
Match detection
r
r+1
; Sets P7FC0 to "1"
; Sets P7CR0 to "1"
; Sets TC001EN to "1"
; Sets the interrupt master enable flag to "disable"
; Sets the INTTC00 interrupt enable register to "1"
; Sets the interrupt master enable flag to "enable"
; Selects the 8-bit PPG mode and fcgck/2
; Sets the timer register (cycle)
; 32μs / (2/fcgck) = 0xA0
; Sets the timer register (duty pulse)
; 8μs / (2/fcgck) = 0x28
; Starts TC00
(Duty pulse)
s
Counter
clear
0
r
1
(1 cycle)
Write t
t
s
Match detection
Match detection
r
Write w
r+1
w
(Duty pulse)
s
s
w
Counter
clear
0
t
1
(1 cycle)
w
Match detection
t
Timer stop
t+1
TMP89CM42
w
Counter
clear
Returns to the
level selected
at TFF0
0
1
0