tmp89cm42 TOSHIBA Semiconductor CORPORATION, tmp89cm42 Datasheet - Page 24

• Manufacturer Part Number: tmp89cm42
• Description: 8 Bit Microcontroller Tlcs-870/c1 Series
• Manufacturer: TOSHIBA Semiconductor CORPORATION

2.2
Memory space
RB000
System control register 3
System control register 4
(0x0FDE)
(0x0FDF)
SYSCR3
SYSCR4
2.2.1.1
Note 1: The value of SYSCR3<RAREA> is invalid until 0xD4 is written into SYSCR4.
Note 2: To assign vector address areas to RAM, set SYSCR3<RVCTR> to "1" and SYSCR3<RAREA> to "1".
Note 3: Bits 7 to 3 of SYSCR3 are read as "0".
Note 1: SYSCR4 is a write-only register, and must not be accessed by using a read-modify-write instruction, such as a bit oper-
Note 2: After SYSCR3<RSTDIS> is modified, SYSCR4 should be written 0xB2 (Enable code for SYSCR3<RSTDIS>) in NORMAL
Note 3: After IRSTSR<FCLR> is modified, SYSCR4 should be written 0x71 (Enable code for IRSTSR<FCLR> in NORMAL mode
0x083F in the code area to execute the program.
instructions and interrupt except reset can be mapped to RAM.
SYSCR4
Read/Write
Bit Symbol
Read/Write
After reset
ation.
mode when fcgck is fc/4 (CGCR<FCGCKSEL>=00). Otherwise, SYSCR3<RSTDIS> may be enabled at unexpected tim-
ing.
when fcgck is fc/4 (CGCR<FCGCKSEL>=00). Otherwise, IRSTSR<FCLR> may be enabled at unexpected timing.
Bit Symbol
RAREA
RVCTR
The RAM is mapped in the data area immediately after reset release.
By setting SYSCR3<RAREA> to "1" and writing 0xD4 to SYSCR4, RAM can be mapped to 0x0040to
At this time, by setting SYSCR<RVCTR> to "1" and writing 0xD4 to SYSCR4, vector table for vector call
After reset
RAM
Note 1: When the RAM is not mapped in the code area, the SWI instruction is fetched from 0x0040 to 0x083F.
Note2: The contents of the RAM become unstable when the power is turned on and immediately after a reset
Writes the SYSCR3 data control
code.
Specifies mapping of the RAM in
the code area
Specifies mapping of the vector ta-
ble for vector call instructions and
interrupts
is released. To execute the program by using the RAM, transfer the program to be executed in the
initialization routine.
7
0
R
7
0
-
6
0
R
6
0
-
5
0
0xD4 :
R
0xB2 :
5
0
0x71 :
-
Page 10
0 :
1 :
0 :
1 :
The RAM is not mapped from 0x0040 to 0x083F in the code area.
The RAM is mapped from 0x0040 to 0x083F in the code area.
Vector table for vector call instruc-
tions
0xFFA0 to 0xFFBF in the code area
0x01A0 to 0x01BF in the code area
Enables the contents of SYSCR3<RSTDIS>.
Enables the contents of SYSCR3<RAREA> and SYSCR3 <RVCTR>.
Enables the contents of IRSTSR<FCLR>
Others : Invalid
4
0
R
4
0
-
SYSCR4
W
3
0
R
0
3
-
RVCTR
R/W
2
0
2
0
Vector table for interrupt
0xFFCC to 0xFFFF in the code area
0x01CC to 0x01FD in the code area
RAREA
R/W
1
0
1
0
TMP89CM42
(RSTDIS)
R/W
0
0
0
0