se97pw/1 NXP Semiconductors, se97pw/1 Datasheet - Page 35

• Manufacturer Part Number: se97pw/1
• Description: Se97 Memory Module Temp Sensor With Integrated Spd
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 29.
V
The AC specifications fully meet or exceed SMBus 2.0 specifications, but allow the bus to interface with the I
to 400 kHz.
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
SE97_2
Product data sheet
Symbol
EEPROM power-up timing
t
t
Write cycle limits
T
pu(R)
pu(W)
DD
Fig 36. Definition of timing for F/S-mode devices on the I
cy(W)
= 1.7 V to 3.6 V; T
Delay from SDA STOP to SDA START.
Delay from SDA START to first SCL HIGH-to-LOW transition.
Delay from SCL HIGH-to-LOW transition to SDA edges.
Delay from SCL LOW-to-HIGH transition to restart SDA.
These parameters tested initially and after a design or process change that affects the parameter.
t
The write cycle time is the time elapsed between the STOP command (following the write instruction) and the completion of the internal
write cycle. During the internal write cycle, SDA is released by the slave and the device does not acknowledge external commands.
A device must internally provide a hold time of at least 200 ns for SDA signal (referenced to the V
undefined region of the falling edge of SCL.
pu(R)
SDA
SDA
SCL
SCL
and t
V
V
IL
IH
Parameter
read power-up time
write power-up time
write cycle time
SMBus AC characteristics
= 0.3V
t
= 0.7V
SU;STA
70 %
pu(W)
30 %
S
t
t
are the delays required from the time V
DD
HD;STA
DD
f
amb
t
f
70 %
30 %
= 20 C to +125 C; unless otherwise specified. These specifications are guaranteed by design.
Sr
1
[5]
st
1 / f
clock cycle
t
r
SCL
t
HD;STA
t
HD;DAT
70 %
30 %
…continued
70 %
30 %
t
SP
t
SU;DAT
Conditions
Rev. 02 — 12 October 2007
DD
t
is stable until the specified operation can be initiated.
r
70 %
30 %
70 %
30 %
t
VD;ACK
2
C-bus
t
Memory module temp sensor with integrated SPD
LOW
9
th
[6]
[6]
[7]
clock
V
DD
t
HIGH
t
SU;STO
Min
= 1.7 V to 3.6 V
-
-
-
70 %
30 %
t
VD;DAT
P
Max
1
1
5
IH(min)
t
BUF
V
of the SCL signal) to bridge the
DD
S
Min
= 3.0 V to 3.6 V Unit
-
-
-
© NXP B.V. 2007. All rights reserved.
9
2
th
C-bus from DC
002aac938
clock
Max
SE97
1
1
5
cont.
cont.
35 of 43
ms
ms
ms