se97pw/1 NXP Semiconductors, se97pw/1 Datasheet - Page 5

• Manufacturer Part Number: se97pw/1
• Description: Se97 Memory Module Temp Sensor With Integrated Spd
• Manufacturer: NXP Semiconductors

NXP Semiconductors
7. Functional description
SE97_2
Product data sheet
Fig 4. Slave address
MSB
0
a. Temperature sensor
0
fixed
slave address
1
1
7.1 Serial bus interface
7.2 Slave address
7.3 EVENT output
A2
selectable
hardware
The SE97 communicates with a host controller by means of the 2-wire serial bus
(I
device supports SMBus, I
speed is defined to have bus speeds from 0 Hz to 100 kHz, I
to 400 kHz, and the SMBus is from 10 kHz to 100 kHz. The host or bus master generates
the SCL signal, and the SE97 uses the SCL signal to receive or send data on the SDA
line. Data transfer is serial, bidirectional, and is one byte at a time with the Most Significant
Bit (MSB) is transferred first. Since SCL and SDA are open-drain, pull-up resistors must
be installed on these pins.
The SE97 uses a 4-bit fixed and 3-bit programmable (A0, A1 and A2) 7-bit slave address
that allows a total of eight devices to co-exist on the same bus. The A0, A1 and A2 pins
are pulled LOW internally. The A0 pin is also overvoltage tolerant supporting 10 V
software write protect. When it is driven higher than 7 V, writing a special command would
put the EEPROM in reversible write protect mode (see
Protection”). Each pin is sampled at the start of each I
temperature sensor’s fixed address is ‘0011b’. The EEPROM’s fixed address for the
normal EEPROM read/write is ‘1010b’, and for EEPROM software protection command is
‘0110b’. Refer to
The EVENT pin is an open-drain output whose function can be programmed as an
interrupt, comparator, or critical alarm mode. When the device operates in Interrupt mode,
and the temperature reaches a critical temperature, the device switches to the comparator
mode automatically and asserts the EVENT pin. When the temperature drops below
critical temperature, the device reverts back to either interrupt or comparator mode, as
programmed in the Configuration Register. The interrupt latch can be cleared by writing a
‘1’ to the ‘Clear EVENT’ bit (CEVNT) in the Configuration Register or by performing the
SMBus Alert Response Address (ARA).
The EVENT output is typically pulled up to a voltage level from 0.9 V to 3.6 V with an
external pull-up resistor, but there is no real lower limit on the pull-up voltage for the
EVENT pin since it is simply an open-drain output. It could be pulled up to 0.1 V and
A1
2
C-bus/SMBus) that consists of a serial clock (SCL) and serial data (SDA) signals. The
LSB
002aab304
A0
R/W
X
Figure
MSB
1
b. EEPROM (normal read/write)
Rev. 02 — 12 October 2007
0
fixed
4.
2
C-bus Standard-mode and Fast-mode. The I
slave address
1
0
A2
selectable
hardware
Memory module temp sensor with integrated SPD
A1
LSB
002aab351
A0
R/W
X
2
C-bus/SMBus access. The
Section 7.10.2 “Memory
MSB
0
c. EEPROM (software protection
2
1
command)
C-bus fast speed from 0 Hz
fixed
slave address
1
0
© NXP B.V. 2007. All rights reserved.
2
A2
C-bus standard
selectable
hardware
A1
SE97
LSB
002aab352
A0
R/W
X
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