W83791D Information Storage Devices, Inc, W83791D Datasheet - Page 18

• Manufacturer Part Number: W83791D
• Description: Hardware Monitor With Speech Synthesizer And Asf Functions
• Manufacturer: Information Storage Devices, Inc

6.3 Speech Function
6.3.1
inputs, 17 Hardware Monitor event and 128 programmable software event trigger inputs. If more than two events
happen simultaneously, the priority set by the internal H/W is: SLOTOCC# > EVNTRAP1 > EVNTRAP2 >
EVNTRAP3 > EVNTRAP4 > EVNTRAP5 > TRIGREG(Index 09h) 128 events > VIN0 > VIN1> others (VIN2 –
VIN9,TEMP, FAN, case open). Software trigger is able to accommodate 128 event triggers, with timeout register
(index 08h) enabled in advance for allowance of time on detecting devices. That is, once the system’s power is on,
BIOS can fill trigger event and speech voice will not be sent till the system fails owing to timeout. In addition, to
prevent events from taking place simultaneously.
6.3.2
and speech will clear FIFO queue after service. Coding of Speech program must assign correct CPU_MODE event
vector to issue correct speech voices correspondent to speech trigger events. For example, CPU_MODE event
vector =1 represents absence of CPU, then coding speech with CPU is absent voice. When W83791D detects no
CPU exists, it will send vector = 1 to speech synthesizer and play this voice data. Following is the block diagram of
the 8-Byte event trigger queue.
SCL
SDA
(b) Serial bus read from a register
(Continued)
(Continued)
The W83791D is a derivative of Winbond's PowerSpeech
W83791D provides 8 byte FIFO queue to store event trigger, i.e, the first 8 event can be served by speech
General Description
Event Trigger Queue
SCL
SDA
Repeat
start
by
Master
CLK 1 HZ
Start By
Master
0
0
Timeout Register
8-bit Counter
(Index 08h)
0
0
8-Byte Event Trigger Queue
1
Trigger
Serial Bus Address Byte
1
0
Figure 2. Serial Bus Read from Internal Address Register
Serial Bus Address Byte
Frame 3
0
1
Figure 3. Event trigger Queue
Frame 1
1
1
1
0
0
1
11
1
R/W
Comparator
0
7
Timeout
791D
Ack
7
R/W
0
by
8
791D
Ack
TM
by
8
0
D7
synthesizers. There are up to 5 hardware trigger
0
D7
D6
Data Byte
Frame 4
D6
D5
Publication Release Date: Aug, 2001
Internal Index Register Byte
D5
Enable Timeout
(Index 09h, b6~0)
D4
(Index 0Ah, b6)
Frame 2
Trigger Data
TRIG_REG
D4
D3
Event
D3
D2
D2
D1
D1
W83791D
7
D0
Preliminary
Revision 0.41
7
D0
Master
8
Ack
by
791D
8
Ack
Stop by
Master
by