tc94a58fg TOSHIBA Semiconductor CORPORATION, tc94a58fg Datasheet - Page 8

• Manufacturer Part Number: tc94a58fg
• Description: Single-chip Cd Processor With Built-in Controller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Pin
No.
64
1
2
3
4
5
6
7
P5-1/S10
P5-2/S11
P5-3/S12
P6-0/S13
P6-1/S14
P6-2/S15
P6-3/S16
P5-0/S9
/LRCKin
Symbol
(BRK3)
(BRK4)
(BRK5)
(BRK6)
(BRK7)
(BRK8)
(BRK9)
/AOUT
/ADin1
/DOUT
/BCKin
/ADin2
/ADin3
/SBOK
/ADin4
/LRCK
/CLCK
/BCK
/IPF
/LCD segment output
/LCD segment output
/LCD segment output
/CD processor
/CD processor
I/O port 5-0
Pin Name
I/O port 5
I/O port 6
function
function
● BCK: Bit clock output pin. One of three
● LRCK: LR channel clock output pin. For the L
● AOUT: Audio data output pin. Either MSB first
● DOUT: Digital data output pin. It drives data at
● IPF:
● SBOK: CRCC test result output pin for
● CLCK: Clock input/output pin for reading
● DATA: Subcode P to W data output pin.
● SFSY: Frame sync signal output pin for
● SBSY: Block sync signal output pin for
● BCKin: Bit clock input pin for 1-bit DAC.
● LRCKin: LR channel clock input pin for 1-bit
(Note) Interrupts should not be enabled when
(Note) Unlike other CD processor pins, LRCKin
P6-0 to P6-3 pins have multiplexed functions for
the on-chip 6-bit 4-channel AD converter analog
input. The on-chip AD converter uses
successive approximation. The conversion time
is 242 µ s when the 16.9344-MHz crystal
oscillator is used and 7 instruction cycles
(280 µ s) when the 75-kHz crystal oscillator is
used. The program can specify necessary pins
for AD analog input on a per bit basis. The
internal power supply (MV
reference voltage. When the P6-0 to P6-3 pins
are used as I/O port input, each pin can be
pulled up or down by program.
CD processor operation is undefined.
and BCKin are configured as a pair so
their functions are always switched
together. When these pins are used,
they should be set as I/O port input.
frequencies, 32, 48 or 64 can be
specified using a CD command.
At normal speed: 32 f
channel, this pin drives a low level. For
the R channel, it drives a high level.
The polarity can be inverted using a
CD command.
At normal speed: 44.1 kHz
or LSB first can be specified using a
CD command.
up to double speed (complying with
CP-1201).
Correction flag output pin. If the AOUT
output is C2 error detection/correction,
a high level appears to indicate an
uncorrectable symbol. (Also called
C2PO)
subcode Q data. A high level appears
when the data has passed the test.
subcode P to W data. The input/output
polarity can be inverted using a CD
command.
playback.
subcode. When a subcode sync is
detected, a high level appears at S1.
The controller enables CD interrupts.
When an interrupt occurs on the falling
edge of the SBSY signal, the program
jumps to address 2.
DAC
Function and Operation
8
(Continued on next page)
DD
) is used as the
s
= 1.4112 MHz
instruction
instruction
instruction
Release
Release
MV
enable
enable
Input
Input
Input
DD
R
IN1
Remarks
TC94A58FG
MV
2005-12-7
SS
MV
MV
MV
LCD
voltage
LCD
voltage
AD input
LCD
voltage
MV
MV
MV
DD
DD
DD
DD
DD
DD