at32uc3b0512-z2ues ATMEL Corporation, at32uc3b0512-z2ues Datasheet - Page 255

• Manufacturer Part Number: at32uc3b0512-z2ues
• Description: 32-bit Avr Microcontroller
• Manufacturer: ATMEL Corporation

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32059J–12/2010
OVRE: Overrun Error (clear on read)
GACC: General Call Access (clear on read)
SVACC: Slave Access (automatically set / reset)
SVREAD: Slave Read (automatically set / reset)
TXRDY: Transmit Holding Register Ready (automatically set / reset)
RXRDY: Receive Holding Register Ready (automatically set / reset)
NACK used in Master mode:
0 = Each data byte has been correctly received by the far-end side TWI slave component.
1 = A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP.
NACK used in Slave Read mode:
0 = Each data byte has been correctly received by the Master.
1 = In read mode, a data byte has not been acknowledged by the Master. When NACK is set the programmer must not fill THR
Note that in Slave Write mode all data are acknowledged by the TWI.
This bit is only used in Master mode.
0 = RHR has not been loaded while RXRDY was set
1 = RHR has been loaded while RXRDY was set. Reset by read in SR when TXCOMP is set.
This bit is only used in Slave mode.
0 = No General Call has been detected.
1 = A General Call has been detected. After the detection of General Call, the programmer decoded the commands that follow
GACC behavior can be seen in
This bit is only used in Slave mode.
0 = TWI is not addressed. SVACC is automatically cleared after a NACK or a STOP condition is detected.
1 = Indicates that the address decoding sequence has matched (A Master has sent SADR). SVACC remains high until a NACK
SVACC behavior can be seen in
This bit is only used in Slave mode. When SVACC is low (no Slave access has been detected) SVREAD is irrelevant.
0 = Indicates that a write access is performed by a Master.
1 = Indicates that a read access is performed by a Master.
SVREAD behavior can be seen in
TXRDY used in Master mode:
0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into THR register.
1 = As soon as a data byte is transferred from THR to internal shifter or if a NACK error is detected, TXRDY is set at the same
TXRDY behavior in Master mode can be seen in
TXRDY used in Slave mode:
0 = As soon as data is written in the THR, until this data has been transmitted and acknowledged (ACK or NACK).
1 = It indicates that the THR is empty and that data has been transmitted and acknowledged.
If TXRDY is high and if a NACK has been detected, the transmission will be stopped. Thus when TRDY = NACK = 1, the
TXRDY behavior in Slave mode can be seen in
0 = No character has been received since the last RHR read operation.
1 = A byte has been received in the RHR since the last read.
RXRDY behavior in Master mode can be seen in
RXRDY behavior in Slave mode can be seen in
even if TXRDY is set, because it means that the Master will stop the data transfer or re initiate it.
and the programming sequence.
or a STOP condition is detected.
19-30 on page
19-30 on page
time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).
programmer must not fill THR to avoid losing it.
and
245
Figure 19-30 on page
and
Figure 19-30 on page
245.
245.
245.
Figure 19-26 on page
Figure 19-24 on page
245.
Figure 19-24 on page
Figure 19-24 on page
Figure 19-25 on page
Figure 19-8 on page
Figure 19-10 on page
242.
241,
241,
Figure 19-25 on page
Figure 19-25 on page
241,
225.
241,
226.
Figure 19-27 on page
Figure 19-28 on page
241,
241,
Figure 19-29 on page 245
Figure 19-29 on page 245
243,
244,
Figure 19-29 on page 245
Figure 19-29 on page
AT32UC3B
and
and
Figure
Figure
255