at32uc3b0512-z2ues ATMEL Corporation, at32uc3b0512-z2ues Datasheet - Page 388

• Manufacturer Part Number: at32uc3b0512-z2ues
• Description: 32-bit Avr Microcontroller
• Manufacturer: ATMEL Corporation

32059J–12/2010
•Detailed description
TXINI
FIFOCON
Figure 22-18. Example of an IN Endpoint with 2 Data Banks
The data is written, following the next flow:
• When the bank is empty, TXINI and FIFOCON are set, what triggers an EPnINT interrupt if
• The user acknowledges the interrupt by clearing TXINI.
• The user writes the data into the current bank by using the USB Pipe/Endpoint nFIFO Data
• The user allows the controller to send the bank and switches to the next bank (if any) by
If the endpoint uses several banks, the current one can be written while the previous one is
being read by the host. Then, when the user clears FIFOCON, the following bank may already
be free and TXINI is set immediately.
An “Abort” stage can be produced when a zero-length OUT packet is received during an IN
stage of a control or isochronous IN transaction. The Kill IN Bank (KILLBK) bit in UECONn is
used to kill the last written bank. The best way to manage this abort is to apply the algorithm rep-
resented on
more details about the KILLBK bit.
TXINE is one.
virtual segment (see
483), until all the data frame is written or the bank is full (in which case RWALL is cleared and
the Byte Count (BYCT) field in UESTAn reaches the endpoint size).
clearing FIFOCON.
SW
write data to CPU
BANK 0
Figure 22-19 on page
”USB Pipe/Endpoint n FIFO Data Register (USBFIFOnDATA)” on page
SW
IN
SW
write data to CPU
389. See
BANK 1
(bank 0)
DATA
”Endpoint n Control Register” on page 445
SW
HW
ACK
SW
write data to CPU
IN
BANK0
AT32UC3B
(bank 1)
DATA
to have
ACK
388