at32uc3b0512-z2ues ATMEL Corporation, at32uc3b0512-z2ues Datasheet - Page 397

• Manufacturer Part Number: at32uc3b0512-z2ues
• Description: 32-bit Avr Microcontroller
• Manufacturer: ATMEL Corporation

22.7.3.11
32059J–12/2010
RXINI
FIFOCON
IN
Management of OUT pipes
(bank 0)
DATA
RXINI
FIFOCON
The user then reads from the FIFO (see
DATA)” on page
(FIFOCONC) bit in UPCONnCLR) to free the bank. If the IN pipe is composed of multiple banks,
this also switches to the next bank. The RXINI and FIFOCON bits are updated in accordance
with the status of the next bank.
RXINI shall always be cleared before clearing FIFOCON.
The Read/Write Allowed (RWALL) bit in UPSTAn is set when the current bank is not empty, i.e.,
the software can read further data from the FIFO.
Figure 22-25. Example of an IN Pipe with 1 Data Bank
Figure 22-26. Example of an IN Pipe with 2 Data Banks
OUT packets are sent by the host. All the data can be written which acknowledges or not the
bank when it is full.
The pipe must be configured and unfrozen first.
The Transmitted OUT Data Interrupt (TXOUTI) bit in UPSTAn is set at the same time as FIFO-
CON when the current bank is free. This triggers a PnINT interrupt if the Transmitted OUT Data
Interrupt Enable (TXOUTE) bit in UPCONn is one.
IN
ACK
HW
(bank 0)
DATA
SW
483) and clears the FIFOCON bit (by writing a one to the FIFO Control Clear
read data from CPU
BANK 0
ACK
HW
SW
SW
read data from CPU
”USB Pipe/Endpoint n FIFO Data Register (USBFIFOn-
IN
BANK 0
IN
(bank 1)
DATA
(bank 0)
DATA
SW
ACK
HW
ACK
HW
AT32UC3B
read data from CPU
read data from CPU
SW
SW
BANK 1
BANK 0
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