at32uc3b0512-z2ues ATMEL Corporation, at32uc3b0512-z2ues Datasheet - Page 441

• Manufacturer Part Number: at32uc3b0512-z2ues
• Description: 32-bit Avr Microcontroller
• Manufacturer: ATMEL Corporation

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32059J–12/2010
STALLEDI: STALLed Interrupt
CRCERRI: CRC Error Interrupt
OVERFI: Overflow Interrupt
NAKINI: NAKed IN Interrupt
NAKOUTI: NAKed OUT Interrupt
UNDERFI: Underflow Interrupt
This bit is set to signal that a STALL handshake has been sent. To do that, the software has to set the STALLRQ bit (by writing a
This bit is cleared when the STALLEDIC bit is written to one. This will acknowledge the interrupt.
This bit is set to signal that a CRC error has been detected in an isochronous OUT endpoint. The OUT packet is stored in the
This bit is cleared when the CRCERRIC bit is written to one. This will acknowledge the interrupt.
This bit is set when an overflow error occurs. This triggers an EPnINT interrupt if OVERFE is one.
For all endpoint types, an overflow can occur during OUT stage if the host attempts to write into a bank that is too small for the
This bit is cleared when the OVERFIC bit is written to one. This will acknowledge the interrupt.
This bit is set when a NAK handshake has been sent in response to an IN request from the host. This triggers an EPnINT
This bit is cleared when the NAKINIC bit is written to one. This will acknowledge the interrupt.
This bit is set when a NAK handshake has been sent in response to an OUT request from the host. This triggers an EPnINT
This bit is cleared when the NAKOUTIC bit is written to one. This will acknowledge the interrupt.
This bit is set, for isochronous IN/OUT endpoints, when an underflow error occurs. This triggers an EPnINT interrupt if
An underflow can occur during IN stage if the host attempts to read from an empty bank. A zero-length packet is then
An underflow can also occur during OUT stage if the host sends a packet while the bank is already full. Typically, the CPU is not
Shall be cleared by writing a one to the UNDERFIC bit. This will acknowledge the interrupt.
This bit is inactive (cleared) for bulk and interrupt IN/OUT endpoints and it means RXSTPI for control endpoints.
one to the STALLRQS bit). This triggers an EPnINT interrupt if STALLEDE is one.
bank as if no CRC error had occurred. This triggers an EPnINT interrupt if CRCERRE is one.
packet. The packet is acknowledged and the RXOUTI bit is set as if no overflow had occurred. The bank is filled with all the
first bytes of the packet that fit in.
interrupt if NAKINE is one.
interrupt if NAKOUTE is one.
UNDERFE is one.
automatically sent by the USBB.
fast enough. The packet is lost.
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