at32uc3b0512-z2ues ATMEL Corporation, at32uc3b0512-z2ues Datasheet - Page 664

• Manufacturer Part Number: at32uc3b0512-z2ues
• Description: 32-bit Avr Microcontroller
• Manufacturer: ATMEL Corporation

31.2.3
31.2.3.1
31.2.3.2
32059J–12/2010
Rev. B
PWM
SPI
1. PWM counter restarts at 0x0001
2. PWM channel interrupt enabling triggers an interrupt
3. PWM update period to a 0 value does not work
4. PWM channel status may be wrong if disabled before a period has elapsed
5. The following alternate C functions PWM[4] on PA16 and PWM[6] on PA31 are not
1. SPI Slave / PDCA transfer: no TX UNDERRUN flag
2. SPI Bad serial clock generation on 2nd chip select when SCBR=1, CPOL=1 and
The PWM counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first
PWM period has one more clock cycle.
Fix/Workaround
- The first period is 0x0000, 0x0001, ..., period
- Consecutive periods are 0x0001, 0x0002, ..., period
When enabling a PWM channel that is configured with center aligned period (CALG=1), an
interrupt is signalled.
Fix/Workaround
When using center aligned mode, enable the channel and read the status before channel
interrupt is enabled.
It is impossible to update a period equal to 0 by the using the PWM update register
(PWM_CUPD).
Fix/Workaround
Do not update the PWM_CUPD register with a value equal to 0.
Before a PWM period has elapsed, the read channel status may be wrong. The CHIDx-bit
for a PWM channel in the PWM Enable Register will read '1' for one full PWM period even if
the channel was disabled before the period elapsed. It will then read '0' as expected.
Fix/Workaround
Reading the PWM channel status of a disabled channel is only correct after a PWM period
has elapsed.
available on Rev B
The following alternate C functions PWM[4] on PA16 and PWM[6] on PA31 are not available
on Rev B.
Fix/Workaround
Do not use these PWM alternate functions on these pins.
There is no TX UNDERRUN flag available, therefore in SPI slave mode, there is no way to
be informed of a character lost in transmission.
Fix/Workaround
For PDCA transfer: none.
CNCPHA=0
When multiple CS are in use, if one of the baudrate equals to 1 and one of the others
doesn’t equal to 1, and CPOL=1 and CPHA=0, then an additional pulse will be generated on
SCK.
AT32UC3B
664