at32uc3b0512-z2ues ATMEL Corporation, at32uc3b0512-z2ues Datasheet - Page 435
at32uc3b0512-z2ues
Manufacturer Part Number
at32uc3b0512-z2ues
Description
32-bit Avr Microcontroller
Manufacturer
ATMEL Corporation
Datasheet
1.AT32UC3B0512-Z2UES.pdf
(680 pages)
- Current page: 435 of 680
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22.8.2.8
Register Name:
Access Type:
Offset:
Reset Value:
•
•
32059J–12/2010
EPRSTn: Endpoint n Reset
EPENn: Endpoint n Enable
31
23
15
7
-
-
-
-
Writing a one to this bit will reset the endpoint n FIFO prior to any other operation, upon hardware reset or when a USB bus
All the endpoint mechanism (FIFO counter, reception, transmission, etc.) is reset apart from the Data Toggle Sequence field
The endpoint configuration remains active and the endpoint is still enabled.
Writing a zero to this bit will complete the reset operation and start using the FIFO.
This bit is cleared upon receiving a USB reset.
1: The endpoint n is enabled.
0: The endpoint n is disabled, what forces the endpoint n state to inactive (no answer to USB requests) and resets the endpoint
reset has been received. This resets the endpoint n registers (UECFGn, UESTAn, UECONn) but not the endpoint
configuration (ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE).
(DTSEQ) which can be cleared by setting the RSTDT bit (by writing a one to the RSTDTS bit).
n registers (UECFGn, UESTAn, UECONn) but not the endpoint configuration (ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE).
Endpoint Enable/Reset Register
EPRST6
EPEN6
30
22
14
6
-
-
UERST
Read/Write
0x001C
0x00000000
EPRST5
EPEN5
29
21
13
5
-
-
EPRST4
EPEN4
28
20
12
4
-
-
EPRST3
EPEN3
27
19
11
3
-
-
EPRST2
EPEN2
26
18
10
2
-
-
EPRST1
EPEN1
25
17
9
1
-
-
AT32UC3B
EPRST0
EPEN0
24
16
8
0
-
-
435
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