p89lpc9351 NXP Semiconductors, p89lpc9351 Datasheet - Page 49

• Manufacturer Part Number: p89lpc9351
• Description: 8-bit Microcontroller With Accelerated Two-clock 80c51 Core 8 Kb 3 V Byte-erasable ?ash With 8-bit Adc
• Manufacturer: NXP Semiconductors

NXP Semiconductors
P89LPC9351_1
Preliminary data sheet
7.30.10 Hardware activation of the bootloader
7.30.8 ISP
7.30.9 Power-on reset code execution
7.31 User configuration bytes
ISP is performed without removing the microcontroller from the system. The ISP facility
consists of a series of internal hardware resources coupled with internal firmware to
facilitate remote programming of the P89LPC9351 through the serial port. This firmware is
provided by NXP and embedded within each P89LPC9351 device. The NXP ISP facility
has made in-system programming in an embedded application possible with a minimum
of additional expense in components and circuit board area. The ISP function uses five
pins (V
interface your application to an external circuit in order to use this feature.
The P89LPC9351 contains two special flash elements: the Boot Vector and the Boot
Status bit. Following reset, the P89LPC9351 examines the contents of the Boot Status bit.
If the Boot Status bit is set to zero, power-up execution starts at location 0000H, which is
the normal start address of the user’s application code. When the Boot Status bit is set to
a value other than zero, the contents of the Boot Vector are used as the high byte of the
execution address and the low byte is set to 00H.
Table 8
bootloader is pre-programmed into the address space indicated and uses the indicated
bootloader entry point to perform ISP functions. This code can be erased by the user.
Remark: Users who wish to use this loader should take precautions to avoid erasing the
1 kB sector that contains this bootloader. Instead, the page erase function can be used to
erase the first eight 64-byte pages located in this sector.
A custom bootloader can be written with the Boot Vector set to the custom bootloader, if
desired.
Table 8.
The bootloader can also be executed by forcing the device into ISP mode during a
power-on sequence (see the P89LPC9351 User manual for specific information). This has
the same effect as having a non-zero status byte. This allows an application to be built that
will normally execute user code but can be manually forced into ISP operation. If the
factory default setting for the boot vector (1FH) is changed, it will no longer point to the
factory pre-programmed ISP bootloader code. After programming the flash, the status
byte should be programmed to zero in order to allow execution of the user’s application
code beginning at address 0000H.
Some user-configurable features of the P89LPC9351 must be defined at power-up and
therefore cannot be set by the program after start of execution. These features are
configured through the use of the flash byte UCFG1 and UCFG2. Please see the
P89LPC9351 User’s Manual for additional details.
Device
P89LPC9351
DD
shows the factory default Boot Vector setting for these devices. A factory-provided
, V
Default boot vector values and ISP entry points
SS
, TXD, RXD, and RST). Only a small connector needs to be available to
Default
boot vector
1FH
Rev. 01 — 19 November 2008
Default
bootloader
entry point
1F00H
8-bit microcontroller with 8-bit ADC
Default bootloader
code range
1E00H to 1FFFH
P89LPC9351
© NXP B.V. 2008. All rights reserved.
1 kB sector
range
1C00H to 1FFFH
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