p89lpc9351 NXP Semiconductors, p89lpc9351 Datasheet - Page 52

• Manufacturer Part Number: p89lpc9351
• Description: 8-bit Microcontroller With Accelerated Two-clock 80c51 Core 8 Kb 3 V Byte-erasable ?ash With 8-bit Adc
• Manufacturer: NXP Semiconductors

NXP Semiconductors
P89LPC9351_1
Preliminary data sheet
8.6.1 Fixed channel, single conversion mode
8.6.2 Fixed channel, continuous conversion mode
8.6.3 Auto scan, single conversion mode
8.6.4 Auto scan, continuous conversion mode
8.6.5 Dual channel, continuous conversion mode
8.6 ADC operating modes
A single input channel can be selected for conversion. A single conversion will be
performed and the result placed in the result register pair which corresponds to the
selected input channel. An interrupt, if enabled, will be generated after the conversion
completes.
In fixed channel mode, the PGA channel selection is dependent on the ADC channel
selection. If PGA is enabled, all the selected channels for A/D conversion will be amplified
and the gain amplify level is the same.
A single input channel can be selected for continuous conversion. The results of the
conversions will be sequentially placed in the four result register. The user may select
whether an interrupt can be generated after every four conversions. Additional conversion
results will again cycle through the four result register, overwriting the previous results.
Continuous conversions continue until terminated by the user.
In fixed channel mode, the PGA channel selection is independent and can be different to
A/D conversion channel selection. If different, the gain of the selected ADC channel is 1.
Any combination of the four input channels can be selected for conversion. A single
conversion of each selected input will be performed and the result placed in the result
register which corresponds to the selected input channel. An interrupt, if enabled, will be
generated after all selected channels have been converted. If only a single channel is
selected this is equivalent to single channel, single conversion mode.
In auto scan mode, the PGA channel selection is dependent on the ADC channel
selection. If PGA is enabled, all the selected channel for A/D conversion will be amplified
and the gain amplify level is the same.
Any combination of the four input channels can be selected for conversion. A conversion
of each selected input will be performed and the result placed in the result register which
corresponds to the selected input channel. An interrupt, if enabled, will be generated after
all selected channels have been converted. The process will repeat starting with the first
selected channel. Additional conversion results will again cycle through the eight result
register pairs, overwriting the previous results. Continuous conversions continue until
terminated by the user.
In auto scan mode, the PGA channel selection is dependent on the ADC channel
selection. If PGA is enabled, all the selected channel for A/D conversion will be amplified
and the gain amplify level is the same.
This is a variation of the auto scan continuous conversion mode where conversion occurs
on two user-selectable inputs. The result of the conversion of the first channel is placed in
the result register, ADxDAT0. The result of the conversion of the second channel is placed
in result register, ADxDAT1. The first channel is again converted and its result stored in
Rev. 01 — 19 November 2008
8-bit microcontroller with 8-bit ADC
P89LPC9351
© NXP B.V. 2008. All rights reserved.
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