p89lpc9171fdh NXP Semiconductors, p89lpc9171fdh Datasheet - Page 47

• Manufacturer Part Number: p89lpc9171fdh
• Description: 8-bit Microcontroller With Accelerated Two-clock 80c51 Core, 2 Kb 3 V Byte-erasable Flash With 8-bit Adc
• Manufacturer: NXP Semiconductors

NXP Semiconductors
P89LPC9151_61_71_2
Product data sheet
7.17.2 Power-down mode
7.17.3 Total Power-down mode
7.18 Reset
The Power-down mode stops the oscillator in order to minimize power consumption. The
P89LPC9151/9161/9171 exits Power-down mode via any reset, or certain interrupts. In
Power-down mode, the power supply voltage may be reduced to the data retention supply
voltage V
entered. SFR contents are not guaranteed after V
it is highly recommended to wake-up the processor via reset in this case. V
raised to within the operating range before the Power-down mode is exited.
Some chip functions continue to operate and draw power during Power-down mode,
increasing the total power used during power-down. These include: Brownout detect,
watchdog timer, comparators (note that comparators can be powered down separately),
and RTC/system timer. The internal RC oscillator is disabled unless both the RC oscillator
has been selected as the system clock and the RTC is enabled.
This is the same as Power-down mode except that the brownout detection circuitry and
the voltage comparators are also disabled to conserve additional power. The internal RC
oscillator is disabled unless both the RC oscillator has been selected as the system clock
and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during
power-down, there will be high power consumption. Please use an external low frequency
clock to achieve low power with the RTC running during power-down.
The P1.5/RST pin can function as either a LOW-active reset input or as a digital input,
P1.5. The Reset Pin Enable (RPE) bit in UCFG1, when set to logic 1, enables the external
reset input function on P1.5. When cleared, P1.5 may be used as an input pin.
Remark: During a power-up sequence, the RPE selection is overridden and this pin
always functions as a reset input. An external circuit connected to this pin should not
hold this pin LOW during a power-on sequence as this will keep the device in reset.
After power-up this pin will function as defined by the RPE bit. Only a power-up reset will
temporarily override the selection defined by RPE bit. Other sources of reset will not
override the RPE bit.
Note: During a power cycle, V
to ensure a power-on reset (see
Reset can be triggered from the following sources:
For every reset source, there is a flag in the Reset Register, RSTSRC. The user can read
this register to determine the most recent reset source. These flag bits can be cleared in
software by writing a logic 0 to the corresponding bit. More than one flag bit may be set:
•
•
•
•
•
•
External reset pin (during power-up or if user configured via UCFG1)
Power-on detect
Brownout detect
Watchdog timer
Software reset
UART break character detect reset
DDR
. This retains the RAM contents at the point where Power-down mode was
Rev. 02 — 9 February 2010
DD
Table 16 “Static
must fall below V
P89LPC9151/9161/9171
characteristics”).
DD
POR
8-bit microcontroller with 8-bit ADC
has been lowered to V
before power is reapplied, in order
© NXP B.V. 2010. All rights reserved.
DDR
DD
must be
, therefore
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