p89lpc9171fdh NXP Semiconductors, p89lpc9171fdh Datasheet - Page 51

• Manufacturer Part Number: p89lpc9171fdh
• Description: 8-bit Microcontroller With Accelerated Two-clock 80c51 Core, 2 Kb 3 V Byte-erasable Flash With 8-bit Adc
• Manufacturer: NXP Semiconductors

NXP Semiconductors
P89LPC9151_61_71_2
Product data sheet
7.21.10 The 9
7.21.9 Transmit interrupts with double buffering enabled (modes 1, 2 and 3)
7.22 I
Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = 0), the UART is
compatible with the conventional 80C51 UART. If enabled, the UART allows writing to
SBUF while the previous data is being shifted out. Double buffering is only allowed in
Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled
(DBMOD = 0).
Unlike the conventional UART, in double buffering mode, the TI interrupt is generated
when the double buffer is ready to receive new data.
If double buffering is disabled TB8 can be written before or after SBUF is written, as long
as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until
the bit is shifted out, as indicated by the TI interrupt.
If double buffering is enabled, TB must be updated before SBUF is written, as TB8 will be
double-buffered together with SBUF data.
The I
connected to the bus, and it has the following features:
A typical I
device provides a byte-oriented I
400 kHz.
2
Fig 13. I
•
•
•
•
•
•
C-bus serial interface
Bidirectional data transfer between masters and slaves
Multi master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
The I
2
C-bus uses two wires (SDA and SCL) to transfer information between devices
th
bit (bit 8) in double buffering (modes 1, 2 and 3)
2
2
2
C-bus may be used for test and diagnostic purposes.
C-bus configuration is shown in
C-bus configuration
I
2
C-bus
P1.3/SDA
P89LPC9151/9161/
Rev. 02 — 9 February 2010
9171
P1.2/SCL
2
C-bus interface that supports data transfers up to
P89LPC9151/9161/9171
OTHER DEVICE
WITH I
R P
Figure
INTERFACE
2
C-BUS
13. The P89LPC9151/9161/9171
R P
8-bit microcontroller with 8-bit ADC
OTHER DEVICE
WITH I
INTERFACE
2
C-BUS
002aae576
© NXP B.V. 2010. All rights reserved.
SDA
SCL
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