c8051t617 Silicon Laboratories, c8051t617 Datasheet - Page 21
c8051t617
Manufacturer Part Number
c8051t617
Description
Mixed Signal Byte-programmable Eprom Mcu
Manufacturer
Silicon Laboratories
Datasheet
1.C8051T617.pdf
(210 pages)
- Current page: 21 of 210
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1.1.3. Additional Features
The C8051T61x SoC family includes several key enhancements to the CIP-51 core and peripherals to
improve performance and ease of use in end applications.
The extended interrupt handler provides 14 interrupt sources into the CIP-51, allowing numerous analog
and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention by
the MCU, giving it more effective throughput. The extra interrupt sources are very useful when building
multi-tasking, real-time systems.
Eight reset sources are available: power-on reset circuitry (POR), an on-chip V
when power supply voltage drops below V
Missing Clock Detector, a voltage level detection from Comparator0, a forced software reset, an external
reset pin, and an errant EPROM access circuit. Each reset source except for the POR, Reset Input Pin, or
EPROM error may be disabled by the user in software. The WDT may be permanently enabled in software
after a power-on reset during MCU initialization.
The internal oscillator is factory calibrated to 24.5 MHz ±2%. An external oscillator drive circuit is also
included, allowing an external capacitor, RC, or CMOS clock source to generate the system clock. If
desired, the system clock source may be switched on-the-fly between the internal and external oscillator
circuits. An external oscillator can be extremely useful in low power applications, allowing the MCU to run
from a slow (power saving) external clock source, while periodically switching to the fast internal oscillator
as needed.
EXTCLK
Oscillator
Oscillator
External
Internal
Drive
Px.x
Px.x
Figure 1.4. On-Chip Clock and Reset
Clock Select
System
Clock
Comparator 0
+
-
Detector
Missing
C0RSEF
Clock
(one-
shot)
Microcontroller
EN
Extended Interrupt
RST
CIP-51
Handler
Core
as given in Table 10.2 on page 105), a Watchdog Timer, a
WDT
PCA
Rev. 0.3
EN
VDD
System Reset
C8051T610/1/2/3/4/5/6/7
Supply
Monitor
+
-
Enable
(Software Reset)
SWRSF
'0'
Power On
Reset
Operation
EPROM
Illegal
DD
(wired-OR)
monitor (forces reset
Reset
Funnel
/RST
21
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