c8051t617 Silicon Laboratories, c8051t617 Datasheet - Page 44

• Manufacturer Part Number: c8051t617
• Description: Mixed Signal Byte-programmable Eprom Mcu
• Manufacturer: Silicon Laboratories

C8051T610/1/2/3/4/5/6/7
5.1.
The analog multiplexer (AMUX0) selects the positive input to the ADC, allowing any Port pin to be mea-
sured relative to GND. Additionally, the on-chip temperature sensor or the positive power supply (V
may be selected as the positive ADC input. The ADC0 input channel is selected in the AMX0P register as
described in SFR Definition 5.3. When an external Voltage Reference is supplied to P0.0, the V
supply can be determined by taking a measurement of V
Important Note About ADC0 Input Configuration: Port pins selected as ADC0 inputs should be config-
ured as analog inputs and should be skipped by the Digital Crossbar. To configure a Port pin for analog
input, clear the corresponding bit in register PnMDIN to ‘0’. To force the Crossbar to skip a Port pin, set the
corresponding bit in register PnSKIP to ‘1’. See Section “14. Port Input/Output” on page 116 for more Port
I/O configuration details.
5.2.
The ADC has gain settings of 1x and 0.5x. In 1x mode, the full scale reading of the ADC is determined
directly by V
The 0.5x gain setting can be useful to obtain a higher input Voltage range when using a small V
age, or to measure input voltages that are between V
trolled by the AMP0GN1–0 bits in register ADC0CF.
5.3.
The conversion code format for the ADC is shown below. Conversion codes are represented as 10-bit
unsigned integers. Inputs are measured from ‘0’ to V
tified, depending on the setting of the AD0LJST bit (ADC0CN.0). Conversion codes are represented as 10-
bit unsigned integers.
Inputs are measured from ‘0’ to VREF x 1023/1024. Example codes are shown below for both right-justi-
fied and left-justified data. Unused bits in the ADC0H and ADC0L registers are set to ‘0’.
5.4.
Setting the ADC08BE bit in register ADC0CF to ‘1’ will put the ADC in 8-bit mode. In 8-bit mode, only the 8
MSBs of data are converted. The two LSBs of a conversion are always ‘00’ in this mode. 8-bit conversions
take two fewer SAR clock cycles than 10-bit conversions, so the conversion is completed faster, and a
500 ksps sampling rate can be achieved with a slower SAR clock.
44
V
REF
Input Voltage
(AIN – GND),
Gain = 1
V
V
x 1023/1024
Analog Multiplexer
Gain Setting
Output Coding
8-Bit Mode
REF
REF
0
/2
/4
REF
. In 0.5x mode, the full-scale reading of the ADC occurs when the input voltage is V
Right-Justified ADC0H:ADC0L
(AD0LJST = 0)
0x03FF
0x0200
0x0100
0x0000
Rev. 0.3
REF
REF
x 1023/1024. Data can be right-justified or left-jus-
DD
and V
with the gain setting at 0.5x.
DD
. Gain settings for the ADC are con-
Left-Justified ADC0H:ADC0L
(AD0LJST = 1)
0xFF: 0xFFC0
0x80: 0x8000
0x40: 0x4000
0x00: 0x0000
DD
REF
REF
Voltage
volt-
x 2.
DD
)