c8051t617 Silicon Laboratories, c8051t617 Datasheet - Page 87

• Manufacturer Part Number: c8051t617
• Description: Mixed Signal Byte-programmable Eprom Mcu
• Manufacturer: Silicon Laboratories

SFR Definition 9.4. PSW: Program Status Word
Bit7:
Bit6:
Bit5:
Bits4–3: RS1–RS0: Register Bank Select.
Bit2:
Bit1:
Bit0:
R/W
CY
Bit7
CY: Carry Flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow
(subtraction). It is cleared to logic 0 by all other arithmetic operations.
AC: Auxiliary Carry Flag
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow
from (subtraction) the high order nibble. It is cleared to logic 0 by all other arithmetic opera-
tions.
F0: User Flag 0.
This is a bit-addressable, general purpose flag for use under software control.
These bits select which register bank is used during register accesses.
OV: Overflow Flag.
This bit is set to 1 under the following circumstances: an ADD, ADDC, or SUBB instruction
causes a sign-change overflow, a MUL instruction results in an overflow (result is greater
than 255), or a DIV instruction causes a divide-by-zero condition. The OV bit is cleared to 0
by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other cases.
F1: User Flag 1.
This is a bit-addressable, general purpose flag for use under software control.
PARITY: Parity Flag.
This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the
sum is even.
RS1
0
0
1
1
R/W
AC
Bit6
RS0
0
1
0
1
R/W
Bit5
F0
Register Bank
RS1
R/W
Bit4
0
1
2
3
Rev. 0.3
RS0
R/W
Bit3
0x00–0x07
0x08–0x0F
0x10–0x17
0x18–0x1F
Address
C8051T610/1/2/3/4/5/6/7
R/W
OV
Bit2
R/W
Bit1
F1
(bit addressable)
PARITY
Bit0
R
SFR Address:
00000000
Reset Value
0xD0
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