c8051t617 Silicon Laboratories, c8051t617 Datasheet - Page 60

• Manufacturer Part Number: c8051t617
• Description: Mixed Signal Byte-programmable Eprom Mcu
• Manufacturer: Silicon Laboratories

C8051T610/1/2/3/4/5/6/7
6.
The voltage reference MUX is configurable to use an externally connected voltage reference, the unregu-
lated power supply voltage (V
the Reference Control register (REF0CN) selects the reference source. For an external source, REFSL
should be set to ‘0’; For V
tion, and use the internal regulator as the reference source, the REGOVR bit can be set to ‘1’. See
Figure 6.1 for REF0CN register details. The electrical specifications for the voltage reference circuit are
given in Table 6.1.
Important Note About the V
external voltage reference, P0.0 should be configured as analog input and skipped by the Digital Crossbar.
To configure P0.0 as analog input, set to ‘1’ Bit0 in register P0SKIP. To configure the Crossbar to skip P0.0,
set to ‘1’ Bit0 in register P0SKIP. Refer to Section “14. Port Input/Output” on page 116 for complete Port I/
O configuration details. The external reference voltage must be within the range 0 ≤ V
On C8051T610/1/2/3/6 devices, the temperature sensor connects to the highest order input of the ADC0
positive input multiplexer (see Section “5.1. Analog Multiplexer” on page 44 for details). The TEMPE bit in
register REF0CN enables/disables the temperature sensor. While disabled, the temperature sensor
defaults to a high impedance state and any ADC0 measurements performed on the sensor result in mean-
ingless data.
60
Voltage Reference Options
VDD
GND
R1
Figure 6.1. Voltage Reference Functional Block Diagram
Reference
External
Voltage
Circuit
DD
DD
as the reference source, REFSL should be set to ‘1’. To override this selec-
REF
), or the regulated 1.8 V internal supply (see Figure 6.1). The REFSL bit in
VREF
Input: Port pin P0.0 is used as the external V
VDD
REF0CN
Rev. 0.3
0
1
Regulator
Internal
REGOVR
EN
0
1
Temp Sensor
REF
input. When using an
REF
VREF
(to ADC)
To Analog Mux
≤ V
DD
.