mc9s12xs128 Freescale Semiconductor, Inc, mc9s12xs128 Datasheet - Page 279

• Manufacturer Part Number: mc9s12xs128
• Description: Hcs12 Microcontrollers 16-bit Automotive Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
ETRIGLE
ICLKSTP
ACMPIE
ETRIGP
ETRIGE
ASCIE
AFFC
Field
6
5
4
3
2
1
0
ATD Fast Flag Clear All
0 ATD flag clearing done by write 1 to respective CCF[n] flag.
1 Changes all ATD conversion complete flags to a fast clear sequence.
Internal Clock in Stop Mode Bit — This bit enables A/D conversions in stop mode. When going into stop mode
and ICLKSTP=1 the ATD conversion clock is automatically switched to the internally generated clock ICLK.
Current conversion sequence will seamless continue. Conversion speed will change from prescaled bus
frequency to the ICLK frequency (see ATD Electrical Characteristics in device description). The prescaler bits
PRS4-0 in ATDCTL4 have no effect on the ICLK frequency. For conversions during stop mode the automatic
compare interrupt or the sequence complete interrupt can be used to inform software handler about changing
A/D values. External trigger will not work while converting in stop mode. For conversions during transition from
Run to Stop Mode or vice versa the result is not written to the results register, no CCF flag is set and no compare
is done. When converting in Stop Mode (ICLKSTP=1) an ATD Stop Recovery time t
switch back to bus clock based ATDCLK when leaving Stop Mode. Do not access ATD registers during this time.
0 If A/D conversion sequence is ongoing when going into stop mode, the actual conversion sequence will be
1 A/D continues to convert in stop mode using internally generated clock (ICLK)
External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See
Table 10-7
External Trigger Polarity — This bit controls the polarity of the external trigger signal. See
External Trigger Mode Enable — This bit enables the external trigger on one of the AD channels or one of the
ETRIG3-0 inputs as described in
buffer of this channel is enabled. The external trigger allows to synchronize the start of conversion with external
events. External trigger will not work while converting in stop mode.
0 Disable external trigger
1 Enable external trigger
ATD Sequence Complete Interrupt Enable
0 ATD Sequence Complete interrupt requests are disabled.
1 ATD Sequence Complete interrupt will be requested whenever SCF=1 is set.
ATD Compare Interrupt Enable — If automatic compare is enabled for conversion n (CMPE[n]=1 in ATDCMPE
register) this bit enables the compare interrupt. If the CCF[n] flag is set (showing a successful compare for
conversion n), the compare interrupt is triggered.
0 ATD Compare interrupt requests are disabled.
1 For the conversions in a sequence for which automatic compare is enabled (CMPE[n]=1), ATD Compare
For compare disabled (CMPE[n]=0) a read access to the result register will cause the associated CCF[n] flag
to clear automatically.
For compare enabled (CMPE[n]=1) a write access to the result register will cause the associated CCF[n] flag
to clear automatically.
aborted and automatically restarted when exiting stop mode.
Interrupt will be requested whenever any of the respective CCF flags is set.
for details.
ETRIGLE
0
0
1
1
Table 10-7. External Trigger Configurations
Table 10-6. ATDCTL2 Field Descriptions
S12XS Family Reference Manual, Rev. 1.10
Table
ETRIGP
10-5. If external trigger source is one of the AD channels, the digital input
0
1
0
1
Description
External Trigger Sensitivity
Falling edge
Rising edge
High level
Low level
Analog-to-Digital Converter (ADC12B16CV1)
ATDSTPRCV
Table 10-7
is required to
for details.
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