mc9s12xs128 Freescale Semiconductor, Inc, mc9s12xs128 Datasheet - Page 523

• Manufacturer Part Number: mc9s12xs128
• Description: Hcs12 Microcontrollers 16-bit Automotive Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

18.3.2.8
The FERSTAT register reflects the error status of internal Flash operations.
All flags in the FERSTAT register are readable and only writable to clear the flag.
Freescale Semiconductor
MGSTAT[1:0]
MGBUSY
ACCERR
Offset Module Base + 0x0007
Reset
FPVIOL
RSVD
Field
CCIF
1–0
7
5
4
3
2
W
R
Flash Error Status Register (FERSTAT)
7
0
0
Command Complete Interrupt Flag — The CCIF flag indicates that a Flash command has completed. The
CCIF flag is cleared by writing a 1 to CCIF to launch a command and CCIF will stay low until command
completion or command violation.
0 Flash command in progress
1 Flash command has completed
Flash Access Error Flag — The ACCERR bit indicates an illegal access has occurred to the Flash memory
caused by either a violation of the command write sequence (see
command. While ACCERR is set, the CCIF flag cannot be cleared to launch a command. The ACCERR bit is
cleared by writing a 1 to ACCERR. Writing a 0 to the ACCERR bit has no effect on ACCERR.
0 No access error detected
1 Access error detected
Flash Protection Violation Flag —The FPVIOL bit indicates an attempt was made to program or erase an
address in a protected area of P-Flash or D-Flash memory during a command write sequence. The FPVIOL
bit is cleared by writing a 1 to FPVIOL. Writing a 0 to the FPVIOL bit has no effect on FPVIOL. While FPVIOL
is set, it is not possible to launch a command or start a command write sequence.
0 No protection violation detected
1 Protection violation detected
Memory Controller Busy Flag — The MGBUSY flag reflects the active state of the Memory Controller
0 Memory Controller is idle
1 Memory Controller is busy executing a Flash command (CCIF = 0)
Reserved Bit — This bit is reserved and always reads 0
Memory Controller Command Completion Status Flag — One or more MGSTAT flag bits are set if an error
is detected during execution of a Flash command or during the Flash reset sequence. See
“Flash Command
= Unimplemented or Reserved
0
0
6
Figure 18-12. Flash Error Status Register (FERSTAT)
Description,” and
S12XS Family Reference Manual, Rev. 1.10
Table 18-15. FSTAT Field Descriptions
0
0
5
Section 18.6,
0
0
4
Description
“Initialization” for details.
.
0
0
3
Section
256 KByte Flash Module (S12XFTMR256K1V1)
0
0
2
18.4.1.2) or issuing an illegal Flash
DFDIF
0
1
Section 18.4.2,
SFDIF
0
0
.
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