mc9s12xs128 Freescale Semiconductor, Inc, mc9s12xs128 Datasheet - Page 479

no-image

mc9s12xs128

Manufacturer Part Number
mc9s12xs128
Description
Hcs12 Microcontrollers 16-bit Automotive Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
mc9s12xs128CAA
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
mc9s12xs128CAA
Quantity:
37
Part Number:
mc9s12xs128CAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc9s12xs128CAL
Manufacturer:
FREESCALE
Quantity:
3 050
Part Number:
mc9s12xs128CAL
Manufacturer:
FREESCALE
Quantity:
3 050
Part Number:
mc9s12xs128CAL
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
mc9s12xs128MAA
Manufacturer:
FREESCALE
Quantity:
4 000
Part Number:
mc9s12xs128MAA
Manufacturer:
FREESCALE
Quantity:
5 630
Part Number:
mc9s12xs128MAA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mc9s12xs128MAA
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
mc9s12xs128MAA
0
Part Number:
mc9s12xs128MAA 1M04M
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
mc9s12xs128MAE
Manufacturer:
INITIO
Quantity:
3 310
Part Number:
mc9s12xs128MAL
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
mc9s12xs128VAA
Quantity:
58
16.3.2.15 16-Bit Pulse Accumulator Control Register (PACTL)
When PAEN is set, the PACT is enabled.The PACT shares the input pin with IOC7.
Read: Any time
Write: Any time
Freescale Semiconductor
Module Base + 0x0020
CLK[1:0]
PAMOD
PEDGE
Reset
PAOVI
PAEN
Field
PAI
3:2
6
5
4
1
0
W
R
Pulse Accumulator System Enable — PAEN is independent from TEN. With timer disabled, the pulse
accumulator can function unless pulse accumulator is disabled.
0 16-Bit Pulse Accumulator system disabled.
1 Pulse Accumulator system enabled.
Pulse Accumulator Mode — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1). See
Table
0 Event counter mode.
1 Gated time accumulation mode.
Pulse Accumulator Edge Control — This bit is active only when the Pulse Accumulator is enabled (PAEN = 1).
For PAMOD bit = 0 (event counter mode). See
0 Falling edges on IOC7 pin cause the count to be incremented.
1 Rising edges on IOC7 pin cause the count to be incremented.
For PAMOD bit = 1 (gated time accumulation mode).
0 IOC7 input pin high enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing falling
1 IOC7 input pin low enables M (bus clock) divided by 64 clock to Pulse Accumulator and the trailing rising edge
Clock Select Bits — Refer to
Pulse Accumulator Overflow Interrupt Enable
0 Interrupt inhibited.
1 Interrupt requested if PAOVF is set.
Pulse Accumulator Input Interrupt Enable
0 Interrupt inhibited.
1 Interrupt requested if PAIF is set.
0
0
7
edge on IOC7 sets the PAIF flag.
on IOC7 sets the PAIF flag.
16-19.
Figure 16-24. 16-Bit Pulse Accumulator Control Register (PACTL)
Unimplemented or Reserved
PAEN
0
6
Table 16-18. PACTL Field Descriptions
S12XS Family Reference Manual Rev. 1.10
PAMOD
Table
0
5
16-20.
PEDGE
0
4
Table
Description
16-19.
CLK1
0
3
CLK0
0
2
Timer Module (TIM16B8CV2)
PAOVI
0
1
PAI
0
0
479

Related parts for mc9s12xs128