mc9s12xs128 Freescale Semiconductor, Inc, mc9s12xs128 Datasheet - Page 87

• Manufacturer Part Number: mc9s12xs128
• Description: Hcs12 Microcontrollers 16-bit Automotive Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

1
2.3.20
2.3.21
Freescale Semiconductor
Address 0x0242
Address 0x0243
Read: Anytime.
Write: Anytime.
DDRT
DDRT
DDRT
7-6, 4
Field
Reset
Reset
3-0
5
W
W
R
R
Port T data direction—
This bit determines whether the pin is an input or output.
The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. Else the
routed PWM forces the I/O state to be an output for an enabled channel. In these cases the data direction bit will not
change.
1 Associated pin configured as output
0 Associated pin configured as input
Port T data direction—
This bit determines whether the pin is an input or output.
The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. Else the
routed PWM forces the I/O state to be an output for an enabled channel. Else the VREG_API forces the I/O state to
be an output if enabled. In these cases the data direction bit will not change.
1 Associated pin configured as output
0 Associated pin configured as input
Port T data direction—
This bit determines whether the pin is an input or output.
The TIM forces the I/O state to be an output for a timer port associated with an enabled output compare. In this case
the data direction bit will not change.
1 Associated pin configured as output
0 Associated pin configured as input
DDRT7
RDRT7
Port T Data Direction Register (DDRT)
Port T Reduced Drive Register (RDRT)
0
0
7
7
DDRT6
RDRT6
0
0
6
6
Figure 2-19. Port T Reduced Drive Register (RDRT)
Figure 2-18. Port T Data Direction Register (DDRT)
Table 2-18. DDRT Register Field Descriptions
S12XS Family Reference Manual, Rev. 1.10
DDRT5
RDRT5
0
0
5
5
DDRT4
RDRT4
0
0
4
4
Description
DDRT3
RDRT3
3
0
3
0
RDRT2
DDRT2
0
0
Port Integration Module (S12XSPIMV1)
2
2
DDRT1
RDRT1
Access: User read/write
Access: User read/write
0
0
1
1
DDRT0
RDRT0
0
0
0
0
87
1
1