mcimx50 Freescale Semiconductor, Inc, mcimx50 Datasheet - Page 2

• Manufacturer Part Number: mcimx50
• Description: I.mx50 Applications Processors For Consumer Products
• Manufacturer: Freescale Semiconductor, Inc

Introduction
1.1
The i.MX50 is designed to enable high-tier portable applications by satisfying the performance
requirements of advanced operating systems and applications.
1.1.1
Freescale’s dynamic voltage and frequency scaling (DVFS) allows the device to run at much lower voltage
and frequency with ample processing capacity for tasks, such as audio decode, resulting in significant
power reduction.
1.1.2
The multimedia performance of the i.MX50 processor ARM Cortex-A8 core is boosted by a multi-level
cache system, a NEON co-processor with SIMD media processing architecture and 32-bit single-precision
floating point support, and two vector floating point co-processors. The system is further enhanced by a
programmable smart DMA (SDMA) controller.
1.1.3
The i.MX50 includes support for both standard LCD displays as well as electrophoretic displays (e-paper).
The display subsystem consists of the following modules:
1.1.4
Integrated graphics accelerators offload processing from the ARM processor, enabling high performance
graphic applications at minimum power.
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Electrophoretic Display Controller (EPDC) (i.MX508 only)
The EPDC is a feature-rich, low power, and high-performance direct-drive active matrix EPD
controller. It is specifically designed to drive E-INK
TFT architectures. The goal of the EPDC is to provide an efficient SoC integration of this
functionality for e-paper applications, allowing a significant bill of materials cost savings over an
external solution while reaching much higher levels of performance and lower power. The EPDC
module is defined in the context of an optimized hardware/software partitioning and works in
conjunction with the ePXP (see
Enhanced LCD Controller Interface (eLCDIF)
The eLCDIF is a high-performance LCD controller interface that supports a rich set of modes and
allows interoperability with a wide variety of LCD panels, including DOTCK/RGB and smart
panels. The module also supports synchronous operation with the ePXP to allow the processed
frames to be passed from the ePXP to the eLCDIF through an on-chip SRAM buffer. The eLCDIF
can support up to 32-bit interfaces.
Pixel Processing Pipeline (ePXP)
The ePXP is a high-performance pixel processor capable of 1 pixel/clock performance for
combined operations, such as color-space conversion, alpha blending, gamma mapping, and
Product Overview
Dynamic Performance Scaling
Multimedia Processing Powerhouse
Powerful Display System
Graphics Accelerators
i.MX50 Applications Processors for Consumer Products, Rev. 0
Section 1.1.4, “Graphics
TM
EPD panels, supporting a wide variety of
Accelerators”).
Freescale Semiconductor